Impurity-Doped Gate Electrode Stress for Lower FET On-Resistance
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Solution Overview
Problem
As semiconductor devices become smaller and more performance-oriented, there is a need to further reduce the on-resistance of field effect transistors, which existing stress application methods are unable to effectively achieve.
Innovation Solution
A semiconductor device is designed with a gate electrode layer that contains impurity ions at a higher concentration than the conductive impurities in the source or drain regions, allowing for the application of significant stress to the channel region, thereby improving carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are scaled down for higher performance, then device density and integration are improved, but on-resistance reduction becomes more difficult to achieve
Solution Approach 1:
The patent applies local quality by creating specific impurity concentration gradients within the gate electrode layer. The impurity concentration is optimized at different depths and regions to generate appropriate stress distribution, enabling effective on-resistance reduction even in scaled-down devices where uniform stress application is more challenging.
2Reliability
If impurity ions are introduced into the gate electrode layer at high concentration, then stress application to the channel is enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary action by introducing impurity ions into the gate electrode layer during the gate formation process, before subsequent transistor fabrication steps. This timing allows the impurity concentration to be established early, and the stress effects to be maintained throughout subsequent processing without requiring additional complex steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively reduces the on-resistance of field effect transistors by applying a larger and more uniform stress to the channel region, enhancing carrier mobility and improving the overall performance of semiconductor devices.
Implementation Method 1
by applying stress to a channel in which carriers move, an effective mass of the carriers can be reduced and carrier mobility can be improved
Implementation Method 2
introducing impurity ions into the gate electrode layer
Data Source
AI summary
There is provided a semiconductor device including: a semiconductor substrate; a gate insulating film provided on the semiconductor substrate; a gate electrode layer that is provided on the gate insulating film and contains impurity ions; and source or drain regions that are provided on the semiconductor substrate on both sides of the gate electrode layer and contain conductive impurities, in which a concentration of the impurity ions in the gate electrode layer is higher than concentrations of the conductive impurities in the source or drain regions.