Doped Gate Dielectric Profiles for Threshold Voltage Tuning
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Solution Overview
Problem
As semiconductor devices continue to shrink in size, challenges arise in controlling the threshold voltages of gate structures, leading to inefficiencies in integrating electronic components.
Innovation Solution
The implementation of doped gate dielectric layers with dipole dopants allows for precise control of threshold voltages by individual doping loops, enabling varying threshold voltages in different regions of the gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional gate dielectric layers are used in miniaturized semiconductor devices, then device integration density is improved, but threshold voltage control precision deteriorates
Solution Approach 1:
The patent applies local quality by doping specific regions of the gate dielectric layer with dipole dopants to create spatially varying threshold voltages. Different device regions receive tailored dopant concentrations and types (e.g., nitrogen, fluorine, chlorine) to achieve locally optimized electrical characteristics while maintaining overall high integration density
Solution Approach 2:
The patent changes physical and chemical parameters of the gate dielectric layer by introducing dipole dopants that modify the dielectric's electrical properties. By controlling dopant concentration, distribution depth, and chemical composition, the threshold voltage can be precisely adjusted without changing the physical dimensions of the miniaturized devices
2Manufacturing precision
If multiple doping loops are used to control threshold voltages, then threshold voltage precision is improved, but process complexity increases
Solution Approach 1:
The patent segments the doping process into multiple sequential doping loops, where each loop targets specific device regions with particular dopant types and concentrations. This segmentation allows independent optimization of threshold voltages for different transistor types (e.g., PFET and NFET regions) while maintaining a systematic and controllable process flow
Solution Approach 2:
The patent employs periodic doping loops where dopants are introduced, annealed, and then removed or deactivated in cyclic sequences. This periodic action enables precise control over dopant distribution and activation timing, achieving high threshold voltage precision through repeated, controlled cycles rather than a single complex step
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the integration density of electronic components by providing consistent and adjustable threshold voltages, improving the performance and efficiency of semiconductor devices.
Implementation Method 1
each dipole dopant material may form dipole moments with a material of the interfacial layer
Implementation Method 2
one or more dipole dopant materials are doped into a gate dielectric layer
Data Source
AI summary
In an embodiment, a semiconductor device is provided, which includes a first doped gate dielectric layer and a second doped gate dielectric layer, wherein the first doped gate dielectric layer and the second doped gate dielectric layer comprise a high-k material doped with a dipole dopant. The second doped gate dielectric layer has a second concentration of the first dipole dopant. The concentration of the dipole dopant in the first doped gate dielectric layer is greater than the concentration, and the concentration peak of the dipole dopant in the first doped gate dielectric layer is deeper than the concentration peak of the dipole dopant in the second doped gate dielectric layer. A first gate electrode over the first doped gate dielectric layer, and a second gate electrode over the second doped gate dielectric layer, the first gate electrode and the second gate electrode have a same width.