Doped Insulator Diffusion for 3D NAND Doping Control

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Solution Overview

Problem

Current methods for manufacturing 3D memory devices face challenges in controlling doping concentration in active strips, particularly between string select structures and bit line pad regions, which affects the performance of memory cells.

Innovation Solution

A method involving the formation of semiconductor strips with memory and contact landing areas, where a doped insulating material is deposited and diffused into the strips using a drive-in process to enhance dopant dosage, using PSG, ASG, or BSG films to create n+ or p+ junctions, while memory cell gates block dopant diffusion into the memory region.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional doping methods are used to form active strips, then the manufacturing process is simple, but the doping concentration control is poor

Engineering Contradiction:
Improvedoping concentration controlVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

A doped insulating material layer is introduced as an intermediary between the dopant source and the active strip. This layer serves as a controlled dopant reservoir that releases dopants through diffusion, enabling precise doping concentration control in the active strip while maintaining process simplicity

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The doped insulating material layer is prepared in advance with predetermined dopant concentrations and distributions. This preliminary preparation allows the subsequent diffusion process to achieve precise doping control without complex real-time adjustments during the doping process

Inventive Principle:
Principle #10Preliminary action

2Reliability

If doping is applied uniformly across the entire active strip, then the process is simple, but the performance of specific regions (between SSLs and bit line pads, between SSLs and GSL) is limited

Engineering Contradiction:
Improvememory cell performanceVSAvoiddoping pattern complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The doped insulating material layer is applied selectively to specific regions of the active strip using a mask pattern. This allows different doping concentrations and types to be introduced into different regions (e.g., between SSLs and bit line pads, between SSLs and GSL), optimizing the performance of each region according to its specific functional requirements

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The active strip is divided into multiple functional regions with different doping requirements. The mask pattern segments the doping process to apply appropriate dopant concentrations and types to each segment, enabling optimized performance for each region while maintaining overall process simplicity

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach provides more uniform doping distribution and improved control over dopant concentration, leading to enhanced performance and narrower threshold voltage distribution in 3D NAND structures.

Implementation Method 1

Diffusion of dopant is caused from the doped insulating material into the strip in the portion of the strip

Methodology Applied
Scientific EffectDiffusion: Diffusion

Implementation Method 2

drive-in process that can enhance the dosage of the dopant in the strip by an extra thermal annealing

Methodology Applied
Scientific EffectThermal annealing: Annealing

Data Source

PatentUS9741569B2Forming memory using doped oxide
Publication Date: 2017.08.22 MACRONIX INTERNATIONAL CO LTD
  • US9741569B2 patent drawing
  • US9741569B2 patent drawing
  • US9741569B2 patent drawing

AI summary

A method is provided for manufacturing a memory device. A strip of semiconductor material is formed having a memory region, a contact landing area region and a switch region between the memory region and the contact landing area region. A memory layer is formed on surfaces of the strip in the memory region. A plurality of memory cell gates is formed over the memory region of the strip. A switch gate is formed over the switch region of the strip. A doped insulating material is deposited over a portion of the strip between the contact landing area region and the memory region. Diffusion of dopant is caused from the doped insulating material into the strip in the portion of the strip.