Doped Selection Element Structure for Low-Leakage Memory Cells
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving miniaturization, low power consumption, and high performance while effectively storing data due to issues with current leakage and resistance switching mechanisms in memory cells.
Innovation Solution
The semiconductor device incorporates a memory cell structure with a selection element layer composed of silicon oxide, silicon nitride, or silicon oxynitride, doped with boron, aluminum, gallium, indium, or thallium, and a memory element layer with a magnetic tunnel junction, utilizing plasma doping and ion implantation to enhance electrical conductivity and data storage capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Weight of moving object
If miniaturization is pursued to reduce device size and power consumption, then device size and power consumption are reduced, but current leakage and resistance switching reliability deteriorate
Solution Approach 1:
The patent changes the material parameters of the selection element by doping silicon oxide, silicon nitride, or silicon oxynitride with specific dopants (boron, aluminum, gallium, indium, thallium) in controlled concentrations. This modifies the electrical properties to achieve appropriate resistance values that prevent current leakage while maintaining miniaturization benefits
Solution Approach 2:
The patent employs composite material structures by combining doped semiconductor materials with dielectric materials (silicon oxide, silicon nitride, silicon oxynitride) in the selection element. This composite approach enables simultaneous optimization of electrical conductivity and leakage prevention in miniaturized devices
2Length of moving object
If miniaturization is pursued to reduce device size, then device size is reduced, but resistance switching mechanism reliability deteriorates
Solution Approach 1:
The patent modifies the resistance switching characteristics by adjusting dopant concentration and type in the selection element, changing the electrical parameters to ensure reliable switching behavior even in miniaturized structures where dimensional tolerances are tighter
Solution Approach 2:
The doped selection element acts as an intermediary component between the memory element and external circuitry, mediating the resistance switching signal while compensating for size reduction effects through its tailored electrical properties
3Manufacturing precision
If dopant distribution is stabilized to improve manufacturing precision, then manufacturing precision is improved, but process complexity increases
Solution Approach 1:
The patent performs preliminary doping actions during the material formation stage, incorporating dopants into the silicon-based dielectric layers before final device assembly. This preliminary incorporation simplifies subsequent processing while ensuring uniform dopant distribution throughout the selection element
Solution Approach 2:
The patent merges the doping process with the dielectric layer formation process, combining what would traditionally be separate manufacturing steps into a unified process flow. This integration reduces overall process complexity while achieving precise dopant distribution
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure improves data storage efficiency by stabilizing dopant distribution, reducing current leakage, and enhancing resistance switching, thereby supporting miniaturization and low power consumption in semiconductor devices.
Implementation Method 1
performing a first doping process that provides first dopants into the initial selection element material layer through plasma to reform the initial selection element material layer into a first doped selection element material layer
Implementation Method 2
performing a second doping process that provides second dopants into the first doped selection element material layer through ion implantation to reform the first doped selection element material layer into a second doped selection element material layer
Data Source
AI summary
Memory cell structures, semiconductor memory devices, and their fabrication methods are disclosed. In an embodiment, method for fabricating a semiconductor device includes: forming a lower interconnect over a base layer; forming a memory cell structure over the lower interconnect; and forming an upper interconnect over the memory cell structure, wherein the forming of the memory cell structure includes: forming an initial selection element material layer; performing a first doping process that provides first dopants into the initial selection element material layer to reform the initial selection element material layer into a first doped selection element material layer; performing a second doping process that provides second dopants into the first doped selection element material layer to reform the first doped selection element material layer into a second doped selection element material layer; and forming a selection element layer by patterning the second doped selection element material layer.