Double-Device Data Correction for RAID Memory Read Failures

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Solution Overview

Problem

Existing memory systems with RAID operations are ineffective in correcting read errors when more than one data storage element fails, leading to unreliable performance, data loss, and increased power and resource consumption.

Innovation Solution

Implementing a memory system with two error correction elements, including a parity die and a spare die, to recover data from multiple failed storage elements by using the spare die to replace failed elements and updating parity bits, enabling double device data correction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a memory system uses RAID operations with standard error correction, then single read errors can be corrected, but the system becomes ineffective when more than one data storage element fails

Engineering Contradiction:
Improveerror correction capabilityVSAvoidhandling multiple failures
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The memory system divides error correction into two independent segments: a parity die for correcting read errors and a spare die for replacing failed storage elements. This segmentation allows the system to handle multiple failure scenarios independently, improving both single-error correction and multi-failure handling capabilities

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs preliminary actions by pre-positioning a spare die ready to replace failed storage elements and maintaining parity bits that can be updated in advance. This preliminary preparation enables the system to respond effectively when multiple failures occur, transforming reactive error handling into proactive correction

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the memory system implements robust error correction for multiple failures, then data reliability improves, but power and resource consumption increase

Engineering Contradiction:
Improvedata recovery capabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The error correction system operates autonomously by automatically detecting failures, selecting appropriate correction methods (parity-based or spare-based), and executing recovery without external intervention. This self-service capability reduces the computational and power resources required compared to manual error handling procedures

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The system dynamically changes operational parameters based on failure conditions - switching between parity-based correction mode and spare-based replacement mode. This parameter adaptation allows the system to use minimal resources for simple single failures while reserving full corrective power only when necessary, optimizing overall power consumption

Inventive Principle:
Principle #35Parameter changes

3Ease of operation

If standard RAID operations are used, then simple read errors can be handled, but data loss occurs when multiple storage elements fail

Engineering Contradiction:
Improveerror handling simplicityVSAvoiddata loss
Core Design Contradiction:
Ease of operationVSLoss of information

Solution Approach 1:

The system prepares cushioning measures in advance by maintaining both parity bits and a spare die in the memory architecture. This dual-layer cushioning ensures that when multiple failures occur, data recovery is always possible through either parity reconstruction or spare element replacement, completely preventing data loss while maintaining operational simplicity

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS20250231836A1Double device data correction for redundant- array-of-independent-disks-based systems
Publication Date: 2025.07.17 MICRON TECHNOLOGY INC
  • US20250231836A1 patent drawing
  • US20250231836A1 patent drawing
  • US20250231836A1 patent drawing

AI summary

In some implementations, a memory system may receive a first read command associated with a first memory stripe that includes multiple data storage elements and that is associated with one or more error correction elements. The memory system may perform a first read procedure based on receiving the first read command. The memory system may identify a first read error associated with a first data storage element and may perform a first read error recovery procedure using the one or more error correction elements. The memory system may receive a second read command associated with the first memory stripe. The memory system may perform a second read procedure based on receiving the second read command. The memory system may identify a second read error associated with a second data storage element and may perform a second read error recovery procedure using the one or more error correction elements.