Double-Gate Fin Channel Layout for Dual Conductivity Paths

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Solution Overview

Problem

Current FinFET structures face limitations in further miniaturization and functional development, particularly in forming multiple independent conductivity channels for enhanced transistor performance and packing density.

Innovation Solution

A double-gate four-terminal semiconductor component with two gate electrodes on opposite longitudinal sides of a fin-type channel region, allowing for the formation of two independently controllable conductivity channels through appropriate voltage application, enabling lateral current transport and resonant tunneling between them.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a single gate electrode is used in FinFET structure, then the device can be manufactured with simpler process, but the transistor performance and packing density are limited

Engineering Contradiction:
Improvetransistor packing densityVSAvoidgate electrode configuration
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The single gate electrode is segmented into two separate gate electrodes (first gate electrode and second gate electrode) positioned on opposite longitudinal sides of the channel region. This segmentation enables independent control of two conductivity channels, effectively doubling the transistor functionality within the same footprint area, thus resolving the contradiction between packing density and device complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention transitions from a single-gate configuration to a dual-gate configuration by utilizing the transverse dimension across the channel region. The two gate electrodes are arranged on opposite longitudinal sides, creating conductivity channels that extend in opposite transverse directions. This dimensional approach allows two independent current paths within the same planar footprint, enhancing packing density without proportionally increasing device complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Length of moving object

If the channel region width is reduced for miniaturization, then the device size is reduced, but the formation of multiple independent conductivity channels becomes difficult

Engineering Contradiction:
Improvechannel region dimensionsVSAvoidnumber of conductivity channels
Core Design Contradiction:
Length of moving objectVSProductivity

Solution Approach 1:

The invention utilizes the longitudinal extent of the channel region to accommodate two gate electrodes on opposite sides, each controlling a conductivity channel. By extending the channel region in the longitudinal direction rather than increasing transverse width, the device maintains miniaturization while supporting multiple independent conductivity channels through the dual-gate configuration.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The channel region is functionally segmented into two distinct conductivity channels controlled by separate gate electrodes. This segmentation allows each channel to be independently controlled despite the reduced overall channel dimensions, enabling multiple functional units within a compact structure that satisfies miniaturization requirements.

Inventive Principle:
Principle #1Segmentation

3Productivity

If two gate electrodes are used to form two conductivity channels, then the transistor performance and packing density are improved, but the device structure becomes more complex

Engineering Contradiction:
Improvetransistor packing densityVSAvoidgate electrode and contact region configuration
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The invention merges two field-effect transistor structures into a single integrated device by sharing the common channel region and substrate. The two gate electrodes and four contact regions are configured to create two independently controllable conductivity channels within one device footprint, effectively combining two transistors into one physical structure. This merging approach doubles the functional density without proportionally increasing the overall device complexity.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enables higher packing density of field-effect transistors, efficient control of tunnel currents, and reduced power dissipation, facilitating further miniaturization and functional enhancement of semiconductor components.

Implementation Method 1

The generation and control of conductivity channels in semiconductor components by means of the field effect is well known due to the great industrial importance of field effect transistors (FET)

Methodology Applied
Scientific EffectField effect: Electric Field

Implementation Method 2

Given suitable interconnection and activation in corresponding embodiments, the double-gate four-terminal semiconductor component according to the invention can also realize a lateral current transport by means of a transverse resonant tunneling of charge carriers between the conductivity channels

Methodology Applied
Scientific EffectResonant tunneling: Resonance

Data Source

PatentUS20240186418A1Double-gate four-terminal semiconductor component with fin-type channel region
Publication Date: 2024.06.06 BRANDENBURGISCHE TECH UNIV COTTBUS SENFTENBERG KORPERSCHAFT DES OFFENTLICHEN RECHTS
  • US20240186418A1 patent drawing
  • US20240186418A1 patent drawing
  • US20240186418A1 patent drawing

AI summary

The disclosure relates to a double-gate four-terminal semiconductor component comprising a substrate, an electrically insulating cover layer on the substrate, a fin-type channel region situated above the substrate and composed of a doped semiconductor material of a first conductivity type having two mutually opposite longitudinal sides extending along a longitudinal direction of the channel region, the channel region having a first end and a second end in the longitudinal direction, a first and a second gate electrode, which are situated on the cover layer and are arranged opposite one another each on one of the longitudinal sides of the channel region and are each electrically insulated from the longitudinal sides by an insulation layer, a first and a second contact region situated on the cover layer and composed of a semiconductor material of a second conductivity type.