Double Gate Select Gate Drain Transistors for 3D NAND Leakage Control
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Solution Overview
Problem
In 3D NAND flash memory devices, select gate drain transistors made of polysilicon exhibit greater current leakage compared to their 2D counterparts, leading to issues with programming and reading operations, as electrons can penetrate into unselected memory cell strings, causing unintended programming or incorrect reading.
Innovation Solution
Implementing double gate select gate drain transistors with a front control gate and a back control gate, where both gates can be biased separately or together, to reduce leakage current by increasing the conductance of selected transistors and isolating unselected ones during programming and reading operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 3D NAND structure is used to increase memory density, then memory capacity is improved, but current leakage through select gate drain transistors increases
Solution Approach 1:
The select gate drain transistor is divided into two separate gates: a front control gate and a back control gate. This segmentation allows independent control of each gate, enabling the front gate to handle signal transmission while the back gate suppresses leakage current, thus resolving the contradiction between maintaining memory density and reducing current leakage
Solution Approach 2:
The back control gate acts as an intermediary element that mediates between the front control gate and the channel. By applying appropriate voltages to the back gate, it controls the potential distribution in the channel region, preventing electron penetration into unselected memory cell strings while maintaining the 3D NAND structure's high density advantage
2Ease of manufacture
If polysilicon is used for select gate drain transistor bodies in 3D NAND, then manufacturing is simplified, but current leakage increases compared to single crystal silicon
Solution Approach 1:
The invention changes the electrical parameters of the select gate drain transistor by introducing a dual-gate configuration. This allows optimization of the transistor's electrical characteristics (such as threshold voltage and conductance) independently of the material choice, enabling polysilicon to achieve low leakage performance comparable to or better than single crystal silicon while maintaining manufacturing simplicity
3Productivity
If control gates of multiple strings are connected in rows for efficient addressing, then addressing efficiency is improved, but voltage applied to selected control gates can inadvertently affect unselected memory cells
Solution Approach 1:
The control structure is segmented into front and back control gates for each select gate drain transistor, allowing independent voltage control. This enables the front gate to be connected to control lines for efficient row addressing while the back gate is controlled separately to prevent voltage coupling effects, thus maintaining both addressing efficiency and programming accuracy
Solution Approach 2:
The back control gate serves as an intermediary that decouples the voltage influence between connected control gates. By controlling the back gate voltage, it isolates unselected memory cells from voltage fluctuations on control lines while allowing selected cells to be properly accessed, resolving the contradiction between addressing efficiency and programming accuracy
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of double gate select gate drain transistors effectively reduces current leakage, preventing unintended programming and ensuring accurate read operations by maintaining the isolation of unselected memory cell strings during programming and reading.
Implementation Method 1
double gate select gate drain transistors with a front control gate and a back control gate, where both gates can be biased separately or together, to reduce leakage current by increasing the conductance of selected transistors and isolating unselected ones
Data Source
AI summary
An apparatus, a method, and a system are disclosed. The apparatus includes a string of memory cells coupled to a select gate drain transistor that has a front control gate and a back control gate. The front and back control gates can be coupled together such that they are biased at the same voltage or separate such that they can be biased at different voltages.