Double-Gate SOI RF Structure for Lower Off-Capacitance
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Solution Overview
Problem
Current RF devices on silicon-on-insulator substrates face issues with high off-capacitance (Coff) and parasitic capacitance between source/drain (Cds), which are not adequately low for 5G cellular mobile communication applications.
Innovation Solution
A semiconductor device with a double gate structure is introduced, featuring a buried dielectric layer, first and second gate structures, source/drain regions, and contact structures. The first gate structure is on the front-side, and the second gate structure is on the backside of the dielectric layer, with a trench exposing the second source/drain region for a conductive contact layer, reducing Coff and Cds capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional single gate structure is used on SOI substrate, then the device can be fabricated using standard IC technology, but the off-capacitance and parasitic capacitance are not low enough for 5G applications
Solution Approach 1:
The patent divides the gate structure into two separate gates: a front gate formed on the front surface of the SOI substrate and a back gate formed on the back surface of the SOI substrate. This segmentation allows independent control of the channel from both surfaces, enabling better capacitance control and signal integrity for 5G applications
Solution Approach 2:
The patent transitions from a conventional single-plane gate structure to a three-dimensional dual-plane configuration by placing one gate on the front surface and another gate on the back surface of the SOI substrate, utilizing the vertical dimension to achieve superior electrical characteristics
2Reliability
If the buried dielectric layer is made thicker to reduce parasitic coupling, then the isolation between devices improves, but the fabrication complexity and process difficulty increase
Solution Approach 1:
The patent segments the gate control function into front gate and back gate components, allowing effective device isolation and capacitance control without requiring excessive thickness of the buried dielectric layer, thus maintaining fabrication feasibility
Solution Approach 2:
The patent optimizes the thickness parameters of the buried dielectric layer to a practical range (e.g., 50-200 nm) that provides sufficient isolation while remaining compatible with standard fabrication processes, avoiding the need for excessively thick layers that would complicate manufacturing
Data Source
AI summary
A method of fabricating a semiconductor device is provided. First, a semiconductor structure is provided, and the semiconductor structure includes a buried dielectric layer, a first gate structure disposed on a front-side of the buried dielectric layer, and a first source/drain region and a second source/drain region disposed between the buried dielectric layer and the first gate structure. Then, a trench is formed in the buried dielectric layer. Afterwards, a conductive layer is formed on the buried dielectric layer and in the trench. Finally, the conductive layer is patterned.