Double-Gate TFT Wiring Layout for Lower Signal Delay
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Solution Overview
Problem
The existing oxide semiconductor TFTs with a double gate structure lack a suitable arrangement for electrically connecting the lower and upper gate electrodes, which affects their driving capability and is not adequately addressed in current technologies.
Innovation Solution
An active matrix substrate with a multilayer gate wiring structure, where each gate wiring has multiple contact portions electrically connecting the lower and upper gate electrodes, positioned at intersections with source wirings, optimizing the arrangement to enhance driving capability without increasing load capacitance or reducing aperture ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contact portions are added to electrically connect lower and upper gate electrodes, then driving capability is improved, but load capacitance increases
Solution Approach 1:
The patent applies local quality by strategically positioning contact portions only at specific intersection regions between gate wirings and source wirings, rather than uniformly across the entire structure. This localized approach ensures electrical connection where needed while minimizing overall capacitance increase. The contact portions are placed in intersection regions where they can serve the dual purpose of electrical connection and spatial efficiency.
Solution Approach 2:
The patent implements the skipping principle by having gate wirings extend continuously across pixel regions without interruption, and by positioning contact portions only at necessary intersection points rather than at every possible location. This selective placement reduces the total number of contact portions needed while maintaining effective electrical connection between lower and upper gate electrodes.
2Area of moving object
If contact portions are positioned at intersection regions, then aperture ratio is maintained, but manufacturing complexity increases
Solution Approach 1:
The patent merges multiple functions into the contact portions positioned at intersection regions: they serve as electrical connection points between lower and upper gate electrodes, while simultaneously being located in spaces that would otherwise be unused (intersection regions between gate and source wirings). This merging approach maintains aperture ratio because the contact portions utilize existing spatial intersections rather than occupying additional pixel area.
Solution Approach 2:
The intersection regions where contact portions are placed serve multiple purposes: they provide electrical connection between gate electrodes, they utilize otherwise wasted space in the pixel structure, and they maintain the aperture ratio by not encroaching on the active display area. This multi-functionality reduces the need for separate structural elements.
3Speed
If multiple contact portions are provided per gate wiring, then signal delay is reduced, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the gate wiring into sections separated by contact portions at intersection regions. This segmentation allows the gate signal to be transmitted through multiple parallel paths (via different intersection regions), effectively reducing signal delay without requiring a complete redesign of the gate wiring architecture. The contact portions create intermediate connection points that break up the signal path into manageable segments.
Solution Approach 2:
The patent utilizes the vertical dimension by stacking lower and upper gate electrodes with contact portions connecting them at intersection regions. This three-dimensional arrangement allows multiple contact portions to serve the same gate wiring simultaneously, reducing signal delay through parallel conduction paths while maintaining a compact planar footprint that doesn't significantly increase device complexity.
Data Source
AI summary
An active matrix substrate includes a pixel TFT provided corresponding to each pixel region, a pixel electrode electrically connected to the pixel TFT, a plurality of gate wirings extending in a row direction, and a plurality of source wirings extending in a column direction. Each gate wiring has a multilayer structure including a lower gate wiring electrically connected to a lower gate electrode included in the pixel TFT and an upper gate wiring electrically connected to an upper gate electrode included in the pixel TFT. In a case where the number of the gate wirings is defined as m and the number of the source wirings is defined as n, each gate wiring has 3 or more and less than n contact portions, each contact portion is positioned in any of n intersection regions, and the number of the contact portions overlapping each source wiring is less than m.