Double-Gated 4F2 DRAM Fin Cell for High-Density Current Path Control
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Solution Overview
Problem
The construction and operation of high aspect ratio finFETs are challenging due to the difficulty in forming and controlling gates and transistors with reduced dimensions and spacing, which affects transistor density and manufacturing costs.
Innovation Solution
The formation of upper and lower gates between each fin to create access lines, allowing for the operation of fin transistors by biasing different combinations of these gates to control current paths, and the use of doped regions and trenches to isolate and separate transistors, facilitating the creation of high aspect ratio structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high aspect ratio fins are constructed with reduced width and gap to increase transistor density, then transistor density is improved, but construction and control of gates and transistors becomes increasingly difficult
Solution Approach 1:
The gate structure is segmented into multiple gates (first gate, second gate, third gate, fourth gate) positioned at different heights and locations around the fin. This segmentation allows each gate to independently control current flow through specific portions of the fin, enabling precise control of current paths while maintaining high transistor density with reduced fin width and gap.
Solution Approach 2:
The patent introduces vertical dimensionality by positioning gates at different heights (first and second gates at first height, third and fourth gates at second height). This multi-level gate arrangement in the vertical dimension enables complex current path control without increasing the horizontal footprint, thus maintaining high density while improving manufacturability and control.
2Quantity of substance
If high aspect ratio fins are constructed with reduced width and gap to increase transistor density, then transistor density is improved, but operation and control of the transistors becomes increasingly difficult
Solution Approach 1:
The transistor control is segmented into multiple independent gates that can be biased separately. Each gate (first, second, third, fourth) can independently modulate current flow through different regions of the fin, enabling precise control of current paths and facilitating operation of high-density transistor structures.
Solution Approach 2:
The patent implements dynamic control by allowing different bias conditions on multiple gates to create selectable current paths. By dynamically adjusting gate biases, the system can route current through different fin regions, enabling flexible operation and control of high-density transistor arrays.
Data Source
AI summary
A semiconductor device is provided that includes a fin having a first gate and a second gate formed on a first sidewall of the fin in a first trench, wherein the first gate is formed above the second gate. The device includes a third gate and a fourth gate formed on a second sidewall of the fin in a second trench, wherein the third gate is formed above the fourth gate. Methods of manufacturing and operating the device are also included. A method of operation may include biasing the first gate and the fourth gate to create a current path across the fin.