Double-Implant NOR Flash Memory Structure for Short Channel Effect Control
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Solution Overview
Problem
The reduction in gate linewidth and oxide layer thickness in NOR flash memory structures leads to a weak electric connection at the junction between the highly-doped drain (HDD) and lightly-doped drain (LDD) regions, affecting carrier mobility and increasing the risk of punch-through during the etching process.
Innovation Solution
A double-implant NOR flash memory structure is developed, featuring a semiconductor substrate with two gate structures, an LDD region, deeper first source regions, a HDD region overlapping with the LDD, a P-doped drain region, and a barrier plug to enhance electric connection and prevent punch-through, achieved through specific ion implantation processes and layer formations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate linewidth and oxide layer thickness are reduced to increase device density and driving ability, then the device integration and current driving ability are improved, but the short channel effect becomes more serious
Solution Approach 1:
The LDD region is formed through preliminary ion implantation before the main source/drain formation, creating a shallow junction that prevents punch-through during etching while the subsequent HDD region provides the necessary electrical connection. This preliminary action of forming the LDD region addresses the short channel effect before the device is fully assembled.
Solution Approach 2:
The solution moves from a single-doped-source approach to a dual-doped-approach by introducing both LDD and HDD regions with different doping concentrations and depths. This dimensional change in the doping profile (adding depth and concentration dimensions) allows simultaneous achievement of shallow junction for SCE control and deep connection for carrier mobility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration stabilizes the LDD region during contact hole formation, enhances electric connection, and maintains carrier mobility, resulting in improved reliability and extended service life for NOR flash memory devices.
Implementation Method 1
a highly-doped ion implantation process, so that a highly-doped drain (HDD) region is formed between the two gate structures to overlap with the LDD region
Data Source
AI summary
In a method of manufacturing a double-implant NOR flash memory structure, a phosphorus ion implantation process is performed, so that a P-doped drain region is formed in a semiconductor substrate between two gate structures to overlap with a highly-doped drain (HDD) region and a lightly-doped drain (LDD) region. Therefore, the electric connection at a junction between the HDD region and the LDD region is enhanced and the carrier mobility in the memory is not lowered while the problems of short channel effect and punch-through of LDD region are solved.