Double-Layer Lead Structure for Wafer Level Chip Size Packaging
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Solution Overview
Problem
Conventional wafer level chip size packaging technologies, such as Shellcase type, are limited by a one-layer lead structure, which restricts the number of compatible pads per area and the reliability of electrical connections due to space constraints and thermal expansion mismatches.
Innovation Solution
A double-layer lead structure is introduced, featuring T-, L-, and U-shape junctions between compatible pads and metal layers, allowing for increased pad density and improved electrical connections through additional layout space and stress buffering, with solder bumps attached to the bottom end of the second metal layer for enhanced connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a one-layer lead structure is used in Shellcase type WLCSP, then the package structure is simple and manufacturing is easier, but the number of compatible pads per area is limited and electrical connection reliability is reduced
Solution Approach 1:
The patent transitions from a one-layer lead structure to a double-layer lead structure, adding a vertical dimension to the lead arrangement. The first metal layer is positioned at a first level while the second metal layer is positioned at a second level, creating a three-dimensional configuration that increases pad capacity without proportionally increasing footprint area.
Solution Approach 2:
The lead structure is segmented into two distinct metal layers, each capable of carrying compatible pads. The first metal layer and second metal layer are electrically connected through conductive pathways, allowing the system to function as a unified electrical connection structure while benefiting from the distributed pad arrangement across multiple layers.
2Reliability
If a one-layer lead structure is used, then manufacturing process is simpler, but electrical connection reliability is compromised due to space constraints and thermal expansion mismatches
Solution Approach 1:
By distributing compatible pads across two vertical levels, the patent reduces the thermal and mechanical stress concentration that occurs in single-layer designs. The double-layer configuration provides redundant electrical pathways and distributes thermal expansion forces across different planes, improving overall connection reliability.
Solution Approach 2:
The patent modifies the spatial arrangement parameter of the lead structure by introducing a vertical separation between the first and second metal layers. This parameter change allows for improved stress management and thermal expansion accommodation while maintaining electrical connectivity through the conductive pathways connecting the two layers.
3Productivity
If more compatible pads are accommodated per area, then circuit density increases, but space constraints and thermal expansion mismatches worsen
Solution Approach 1:
The patent resolves the conflict between high circuit density and thermal expansion management by utilizing vertical stacking of metal layers. This three-dimensional arrangement allows for high pad density within a compact footprint while the separation between layers provides space for stress relief and thermal expansion accommodation.
Data Source
AI summary
The present invention disclosed a wafer level chip size packaged chip device with a double-layer lead structure and methods of fabricating the same. The double-layer lead is designed to meet a tendency of increasing quantity per area of peripheral arrayed compatible pads on a semiconductor chip, and also to save more space for layout of lead on the chip bottom surface for avoiding potential short inbetween which happen in increasing probability with increasing quantity per area on the condition of one-layer lead.