Double-Load Instruction for Mixed Stride Data Access

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Solution Overview

Problem

Existing processors face inefficiencies in handling sparse and systematic data sets within machine intelligence applications, as they require distinct loading strategies that current load instructions cannot efficiently accommodate.

Innovation Solution

A processor with a double-load instruction that performs two load operations in a single machine code instruction, one with a fixed stride for systematic data and another with a programmable stride for sparse data, allowing efficient loading of both types of data sets.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single load instruction is used for both sparse and systematic data, then the instruction set remains simple, but the data loading efficiency deteriorates because it cannot handle both sparse and systematic data patterns effectively

Engineering Contradiction:
Improveinstruction set complexityVSAvoiddata loading efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent merges two separate load operations into a single double-load instruction that can load both sparse and systematic data in one execution cycle. The instruction includes fields for both a base address (for systematic data) and an offset (for sparse data), allowing simultaneous access to both data types without requiring multiple instructions.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The double-load instruction is designed as a universal instruction that can handle multiple data loading scenarios: loading only systematic data, loading only sparse data, or loading both simultaneously. The instruction's flexibility allows it to adapt to different data patterns without requiring separate specialized instructions for each case.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If separate load instructions are used for sparse and systematic data, then data loading efficiency improves, but the device complexity increases due to requiring multiple specialized instructions

Engineering Contradiction:
Improvedata loading efficiencyVSAvoidinstruction set complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

Instead of requiring separate instructions for sparse and systematic data loading, the patent combines both functionalities into a single double-load instruction. This merger maintains the efficiency benefits of specialized instructions while reducing the overall instruction set complexity and the number of instructions needed to process mixed data types.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The double-load instruction serves as a universal solution that replaces multiple specialized instructions. By making the instruction multi-functional, it can handle sparse data loading, systematic data loading, and mixed data loading scenarios, thereby improving productivity without increasing device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Productivity

If a fixed stride load instruction is used for systematic data, then loading efficiency improves, but adaptability deteriorates when needing to load sparse data with variable patterns

Engineering Contradiction:
Improvesystematic data loading efficiencyVSAvoiddata pattern adaptability
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The double-load instruction introduces dynamic adaptability by allowing the offset field to be modified by a programmable stride value. While the base address provides fixed stride access for systematic data, the offset can be dynamically adjusted to accommodate variable patterns in sparse data, making the instruction adaptable to different data distributions.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The instruction allows parameter changes by enabling the offset to be updated with a stride value between successive executions. This parameter modification capability allows the same instruction to efficiently handle both fixed-stride systematic data and variable-stride sparse data, improving adaptability without sacrificing systematic data loading efficiency.

Inventive Principle:
Principle #35Parameter changes

4Adaptability or versatility

If a variable stride load instruction is used for sparse data, then adaptability improves, but processing speed deteriorates due to the overhead of calculating variable strides

Engineering Contradiction:
Improvesparse data handling capabilityVSAvoiddata loading speed
Core Design Contradiction:
Adaptability or versatilityVSSpeed

Solution Approach 1:

The stride value for sparse data is pre-loaded into a register before execution. This preliminary action allows the variable stride to be applied directly during the load operation without requiring complex calculations at execution time, thereby maintaining processing speed while achieving the adaptability needed for sparse data patterns.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The offset register acts as an intermediary that stores the programmable stride value. This intermediary mechanism allows the variable stride to be efficiently managed and applied during sparse data loading without introducing significant overhead, balancing adaptability with processing speed.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11061679B2Double-load instruction using a fixed stride and a variable stride for updating addresses between successive instructions
Publication Date: 2021.07.13 GRAPHCORE LTD
  • US11061679B2 patent drawing
  • US11061679B2 patent drawing
  • US11061679B2 patent drawing

AI summary

A processor comprising an execution unit, memory and one or more register files. The execution unit is configured to execute instances of machine code instructions from an instruction set. The types of instruction defined in the instruction set include a double-load instruction for loading from the memory to at least one of the one or more register files. The execution unit is configured so as, when the load instruction is executed, to perform a first load operation strided by a fixed stride, and a second load operation strided by a variable stride, the variable stride being specified in a variable stride register in one of the one or more register files.