Double MIM Trench Capacitor for Low ESR
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Solution Overview
Problem
Existing capacitor structures face limitations in achieving high integration density and controlling serial resistance losses, particularly in applications requiring stable output voltage, such as cellular phones and tablets, due to long interconnection paths and low integration density.
Innovation Solution
A double MIM trench capacitor structure is fabricated using a silicon substrate with a serpentine trench and multilayer stack, where the trench is etched and filled with conductive and dielectric layers, and pads are created on both sides to reduce serial resistivity and increase integration density, allowing for self-stackable capacitor structures with controlled ESR.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If surface mounted device components (SMC) are used externally connected to power supply grid, then capacitor density is increased, but equivalent serial resistance (ESR) losses increase due to long interconnection paths
Solution Approach 1:
The patent transitions from planar surface-mounted capacitor arrangements to three-dimensional vertically stacked trench capacitors. Multiple capacitor electrodes are stacked vertically within trench structures, enabling high capacitor density without increasing lateral interconnection path lengths, thus maintaining low ESR while achieving high integration density.
Solution Approach 2:
The patent implements nested capacitor structures where multiple capacitor electrodes are contained within vertically stacked trench openings in the substrate. This nesting approach allows multiple capacitive elements to occupy a compact vertical space, achieving high density without extending interconnection paths.
2Loss of energy
If capacitor passive technology is integrated into silicon with SIP, then interconnection path length is reduced and ESR losses decrease, but integration density remains relatively low
Solution Approach 1:
The patent achieves high integration density by utilizing the vertical dimension through deeply etched trench structures and vertically stacked capacitor electrodes. This three-dimensional arrangement packs more capacitive elements into the same substrate area while maintaining short lateral interconnection paths for low ESR.
Solution Approach 2:
The patent divides the substrate into multiple trench openings, each containing stacked capacitor electrodes. This segmentation allows parallel integration of multiple capacitor units, increasing overall integration density while each unit maintains short interconnection paths to reduce ESR.
3Quantity of substance
If trench capacitor with multiple conductive layers is used, then integration density is improved, but device complexity increases
Solution Approach 1:
The patent segments the capacitor structure into standardized trench units with repeating patterns of conductive and dielectric layers. This modular segmentation simplifies the fabrication process by using repetitive deposition and etching steps, reducing overall device complexity despite high integration density.
Solution Approach 2:
The patent employs universal substrate and trench structures that can accommodate multiple capacitor units with identical interconnection schemes. This universality simplifies the overall device design and fabrication by using standardized processes across all capacitor elements, managing complexity while achieving high density.
Data Source
Figure 1~2
Figure 3~4
Figure 5~6
AI summary
The invention relates to a capacitor structure (2) comprising a silicon substrate (4) with first and second sides (6, 8), a double double Metal Insulator Metal trench capacitor (10) including a basis electrode (12), an insulator layer (16, 20), a second and a third conductive layers (18, 22); and comprising a second pad (26) and a fourth pad (30) coupled to the basis electrode (12), a first pad (24) and a third pad (28) coupled together, the first pad (24) being located on the same substrate side than the second pad (26), the third pad (28) being located on the same substrate side than the fourth pad (30), the third pad (28) being coupled to the second conductive layer (18), said second conductive layer (18) being flush with or protruding from the opposite second side (8).