Double-Patterned Memory Bit Line Layout for Sub-50nm Precision
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Solution Overview
Problem
Conventional semiconductor memory devices face limitations in forming memory cell arrays with critical dimensions below 50 nm using single patterning, resulting in non-uniform electrical properties due to reduced symmetry in bit lines and active devices.
Innovation Solution
A double-patterned memory cell array layout is implemented using double patterning technology, with alternating patterns of bit lines and a dummy array to achieve increased regularity and uniformity, allowing for bit lines with reduced pitch and uniform electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If single patterning is used to form bit lines, then manufacturing process simplicity is maintained, but manufacturing precision deteriorates due to inability to form patterns with critical dimensions below 50 nm
Solution Approach 1:
The patterning process is divided into two separate exposure steps: first forming a preliminary pattern with relaxed pitch requirements, then forming a second pattern that defines the final high-precision bit line structure. This segmentation allows each exposure step to operate within its optimal resolution capability, achieving sub-50 nm precision without requiring a single ultra-high-resolution exposure step.
2Manufacturing precision
If double patterning is used to reduce pitch, then manufacturing precision improves, but device symmetry deteriorates causing non-uniform electrical properties
Solution Approach 1:
The patent deliberately introduces asymmetric dummy bit lines at the edges of the memory cell array to compensate for the asymmetric effects introduced by double patterning. These dummy structures are positioned specifically to balance the electrical properties (resistance, capacitance) of bit lines across the array, restoring uniformity despite the inherent asymmetry in the double-patterning process.
Solution Approach 2:
Different regions of the bit line array are treated differently: central bit lines follow the standard double-patterning layout, while edge regions incorporate dummy bit lines with specific patterns and spacings tailored to local symmetry requirements. This localized adjustment ensures uniform electrical properties across the entire array without compromising the overall pitch reduction achievement.
3Length of stationary object
If double patterning with alternating patterns is used, then pitch is reduced by half, but manufacturing complexity increases
Solution Approach 1:
The first exposure step creates a preliminary pattern that serves as a template for the second exposure step. This preliminary pattern is intentionally designed with relaxed dimensional requirements, allowing it to be formed with lower precision equipment. The second exposure then uses this template to define the final high-precision bit lines, achieving pitch reduction without requiring both exposure steps to meet the highest precision requirements simultaneously.
Data Source
AI summary
A semiconductor memory device having a double-patterned memory cell array that includes a plurality of first bit lines spaced apart from each other and having a first pattern, a plurality of second bit lines spaced apart from each other and having a second pattern, the second bit lines being between the first bit lines to define an alternating array of first and second bit lines, the first and second patterns being different from each other, a first main memory cell array defined by a first portion of the alternating array, a second main memory cell array defined by a second portion of the alternating array, bit lines in the first main memory cell array having a substantially same regularity as bit lines in the second main memory cell array, and a dummy array between the first main memory cell array and the second main memory cell array.