Double RESURF Semiconductor Device Dimensional Stability
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Solution Overview
Problem
In semiconductor devices with a double RESURF structure, the dimensions of the RESURF structure are proportional to the breakdown voltage, and the process efficiency is reduced due to the separate formation of the body region and RESURF layers using different masks, leading to potential dimensional changes and reduced breakdown voltage.
Innovation Solution
The upper RESURF region is formed to contact a buried region on the semiconductor substrate, with a body region neighboring the field oxide, and both are created using the same mask pattern to maintain dimensional stability and improve process efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the body region and RESURF layer are formed using different masks in separate processes, then the threshold voltage control is achieved, but the process efficiency is reduced and dimensional changes occur due to impurity diffusion
Solution Approach 1:
The patent combines the formation of the body region and RESURF layer into a single ion implantation process using a unified mask pattern. This merging of previously separate processes eliminates the need for multiple masking steps, thereby improving process efficiency while maintaining precise dimensional control of the RESURF structure.
2Reliability
If the body region is formed adjacent to the RESURF layer, then the threshold voltage is controlled, but the dimensions of the RESURF structure change due to impurity diffusion
Solution Approach 1:
The patent performs ion implantation for both the body region and RESURF layer simultaneously in a single process step before any subsequent processing that could cause dimensional changes. This preliminary action ensures that the RESURF structure dimensions are established early and remain stable throughout subsequent manufacturing steps.
Solution Approach 2:
The patent controls the ion implantation parameters (energy, dose, angle) to precisely define the depth and lateral distribution of impurities in both the body region and RESURF layer. By optimizing these parameters, the patent achieves the desired threshold voltage control while maintaining stable RESURF structure dimensions.
3Reliability
If the dimensions of the double RESURF structure are increased to maintain breakdown voltage, then the breakdown voltage is improved, but the area of the transistor increases
Solution Approach 1:
The patent optimizes the doping concentration and depth profiles of both the body region and RESURF layer to achieve the maximum breakdown voltage for a given structure size. By precisely controlling these parameters, the patent extracts the full potential of the double RESURF configuration, achieving high breakdown voltage without requiring excessive dimensional scaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach stabilizes the breakdown voltage by preventing dimensional changes in the RESURF structure and enhances manufacturing efficiency by simultaneous formation of the RESURF and body regions.
Implementation Method 1
the impurities in the body region diffuse in the region of the double RESURF structure
Data Source
AI summary
To provide a semiconductor device capable of suppressing a reduction in breakdown voltage by suppressing a change in dimensions of a double RESURF structure, and a method of manufacturing the same.In the semiconductor device, an upper RESURF region is formed so as to contact with a first buried region on a side of the one main surface within a semiconductor substrate. The semiconductor substrate has a field oxide formed so as to reach the upper RESURF region on the one main surface. The semiconductor substrate includes a second conductivity type body region formed so as to contact with the upper RESURF region on a side of the one main surface and so as to neighbor the field oxide within the semiconductor substrate.