Double-Sided Laminate 3D Interconnects for RF Routing and Isolation
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Solution Overview
Problem
Existing RF front-end modules face challenges with IC metal overlap, difficult isolation requirements, inflexible I/O allocations, and complexity in designing ASWs with multiple poles due to planar structures.
Innovation Solution
Implementing vias as third dimension connections within double-sided laminate packages to establish electric coupling between ICs on opposite sides, utilizing mid-layer ground for shielding and improving routing flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a planar structure is used for RF front-end modules, then the design is simpler, but the routing flexibility is limited and isolation requirements are difficult to meet
Solution Approach 1:
The patent transitions from a two-dimensional planar structure to a three-dimensional structure by utilizing vias to connect metal layers across multiple levels. This dimensional change enables signals to route vertically through the laminate, providing multiple path options and significantly improving routing flexibility while maintaining design manageability through systematic layer organization.
2Ease of manufacture
If I/O allocations are fixed in planar structure, then the design process is easier, but the interconnection length becomes prohibitively long
Solution Approach 1:
By introducing vertical vias through multiple laminate layers, the patent creates three-dimensional interconnection paths that significantly shorten the horizontal distance signals must travel. This allows I/O allocations to be optimized for performance while keeping the design process manageable through structured layer assignments.
Solution Approach 2:
The patent divides the interconnection path into multiple segments across different layers, with each layer handling specific routing functions. This segmentation allows optimization of each segment independently, reducing overall interconnection length while maintaining design systematicity.
3Device complexity
If planar routing is used, then the layout is simpler, but parasitic capacitances increase due to long traces
Solution Approach 1:
The patent reduces parasitic capacitances by routing signals vertically through vias rather than horizontally across long traces. This three-dimensional approach minimizes trace length and associated parasitic effects while maintaining layout simplicity through organized layer assignments and systematic via placement.
Data Source
AI summary
Methods and devices for implementing vias as third-dimension connections in double-sided laminate packages for RF front-end circuits are disclosed. The described methods and devices are based on implementing components of an electronic module in two different integrated circuits and dispose the two integrated circuits on the opposite side of an isolating laminate. The components within one integrated circuit can be coupled to the components on the other integrated circuit by creating vias inside the laminate.