Double-Sided Semiconductor Package With Multi-Interposer Short Interconnects
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Solution Overview
Problem
Semiconductor packages face challenges with increasing complexity, leading to larger sizes, higher ohmic loss, heat generation, and signal delay due to longer interconnect lengths, necessitating improved designs that reduce interconnect lengths and enhance integration.
Innovation Solution
A multi-interposer stacked configuration is employed, integrating optical systems, high-bandwidth memory dies, and logic and control circuits on a single package substrate, using passive and active interposers to reduce interconnect lengths and increase integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If package size is increased to accommodate greater numbers of integrated circuits and dies per package, then integration density is improved, but interconnect length increases leading to higher ohmic loss, heat generation, and signal delay
Solution Approach 1:
The patent transitions from a planar arrangement of integrated circuits and dies to a three-dimensional stacked configuration using multiple interposers. This vertical stacking allows greater integration density while maintaining shorter interconnect paths, as components are connected through vertical vias rather than long horizontal traces.
Solution Approach 2:
The package is divided into multiple segments including first and second interposers, each carrying specific integrated circuits and dies. This segmentation allows independent optimization of interconnect paths within each interposer layer, reducing overall interconnect length compared to a monolithic package structure.
2Quantity of substance
If package size is increased to accommodate greater numbers of integrated circuits and dies per package, then integration density is improved, but interconnect length increases leading to higher signal delay
Solution Approach 1:
By stacking interposers vertically and using through-via connections, the patent reduces signal propagation distance. The three-dimensional architecture enables direct vertical connections between components on different interposers, significantly shortening interconnect length and reducing signal delay compared to planar layouts.
Solution Approach 2:
The interposers serve as intermediary substrates that provide controlled impedance pathways and standardized connection interfaces. These intermediaries enable reliable electrical connections between integrated circuits and dies while maintaining short interconnect lengths through optimized via structures and conductive pathways.
3Quantity of substance
If package size is increased to accommodate greater numbers of integrated circuits and dies per package, then integration density is improved, but interconnect length increases leading to more heat generation
Solution Approach 1:
The vertical stacking architecture distributes heat-generating components across multiple interposer layers rather than concentrating them in a single large plane. This three-dimensional arrangement improves thermal management by creating multiple heat dissipation pathways through the package structure, reducing localized heat accumulation.
Solution Approach 2:
Dividing the package into segmented interposer layers with distributed integrated circuits and dies creates multiple smaller heat sources rather than one large concentrated heat source. This segmentation enables more effective heat dissipation through each interposer substrate and reduces thermal interference between adjacent components.
Data Source
AI summary
An embodiment semiconductor device includes a first die package component, a second interposer electrically coupled to a first side of the first die package component, a third interposer having a voltage regulator circuit electrically coupled to a second side of the first die package component, and an optical component and a high-bandwidth-memory die, each electrically coupled to the second interposer. The first die package component may further include a double-sided semiconductor die, such that a first side of the double-sided semiconductor die is electrically coupled to the second interposer, and a second side of the double-sided semiconductor die is electrically coupled to the third interposer. The first die package component may further include a molding material and a through-molding-via formed in the molding material, such that the through-molding-via provides an electrical connection between the second interposer and the third interposer that bypasses the double-sided semiconductor die.