Double-Sided Semiconductor Package Warpage Control
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Solution Overview
Problem
Current semiconductor manufacturing processes face challenges in producing smaller devices with reduced warpage, which can lead to stresses and reliability issues in semiconductor package assembly, especially with the trend towards smaller and finer pitched conductive traces.
Innovation Solution
A dual-mold method is employed to form a double-sided semiconductor package, utilizing a standardized carrier for singulating semiconductor die and forming build-up interconnect structures with back-side and front-side redistribution layers to minimize warpage and enhance packaging efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are made smaller with finer pitched conductive traces, then device density and performance are improved, but warpage during package assembly increases causing stresses and reliability issues
Solution Approach 1:
The patent divides the semiconductor device into two separate packages, each containing a subset of the total conductive traces. This segmentation allows each package to be manufactured with coarser pitch traces, avoiding the warpage issues associated with fine-pitched traces in a single small device, while still achieving high device density through the combination of both packages.
Solution Approach 2:
The patent transitions from a single-plane two-dimensional layout to a three-dimensional stacked configuration with two separate packages. This dimensional change allows the conductive traces to be distributed across multiple packages rather than compressed into a single small device, reducing trace pitch and warpage while maintaining high density through vertical stacking.
2Volume of moving object
If a single small package is used to maintain small footprint, then device size is reduced, but warpage control becomes difficult leading to cracking and delamination
Solution Approach 1:
The patent segments the single small package into two separate packages, each with a larger individual size that allows for better warpage control during manufacturing. The segmentation distributes the mechanical stresses and allows each package to be manufactured with standard process controls, avoiding the warpage issues that would occur in a single small package.
Solution Approach 2:
The patent creates a composite package structure by combining two separate packages into a single integrated device. This composite structure allows each individual package to maintain optimal dimensions for manufacturing precision and warpage control, while the combined assembly achieves the desired small overall footprint through efficient spatial arrangement.
3Adaptability or versatility
If finer pitched conductive traces are used, then device functionality is enhanced, but manufacturing complexity and difficulty increase
Solution Approach 1:
The patent segments the conductive traces into two separate packages, allowing each package to use coarser pitch traces that are easier to manufacture with standard processes. This segmentation maintains device functionality by distributing the required trace connections across multiple packages rather than requiring fine-pitched traces in a single package.
Solution Approach 2:
The patent resolves the trace pitch complexity issue by moving from a two-dimensional single-plane layout to a three-dimensional stacked configuration. This dimensional change allows trace connections to be established across packages through vertical interconnections rather than requiring extremely fine horizontal pitch, simplifying the manufacturing process while maintaining enhanced device functionality.
Data Source
AI summary
A semiconductor device comprises a first conductive layer formed on a carrier over an insulating layer. A portion of the insulating layer is removed prior to forming the first conductive layer. A first semiconductor die is disposed over the first conductive layer. A discrete electrical component is disposed over the first conductive layer adjacent to the first semiconductor die. A first encapsulant is deposited over the first conductive layer and first semiconductor layer. A conductive pillar is formed through the first encapsulant between the first conductive layer and second conductive layer. A second encapsulant is deposited around the first encapsulant, first conductive layer, and first semiconductor die. A second conductive layer is formed over the first semiconductor die, first encapsulant, and second encapsulant opposite the first conductive layer. The carrier is removed after forming the second conductive layer. A semiconductor package is mounted to the first conductive layer.