Double-Sided Semiconductor Wafer Testing via Redistribution Structures
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Solution Overview
Problem
Current methods for testing semiconductor wafers with through silicon vias (TSVs) are limited by the need for single-sided testing, which restricts the ability to assess the electrical functionality of vias and rear-side redistribution structures effectively, especially in thin wafers with reduced thickness, leading to potential defects and increased assembly costs.
Innovation Solution
A method and apparatus for double-sided testing of semiconductor wafers with a protruding annular rim, utilizing first and second redistribution structures on the front and rear sides, respectively, and a plurality of vias, allowing simultaneous electrical testing from both sides using probes that contact these structures, enabling comprehensive evaluation of via functionality and rear-side processing quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If single-sided testing is used, then the testing process is simple, but the ability to assess via functionality and rear-side redistribution structures is limited
Solution Approach 1:
The patent transitions from single-sided testing to double-sided testing by accessing redistribution structures on both the front and rear sides of the wafer. This dimensional change enables comprehensive evaluation of via functionality and rear-side processing quality that was previously inaccessible, directly resolving the contradiction between testing simplicity and assessment accuracy.
2Length of moving object
If wafer thickness is reduced, then miniaturization is achieved, but the ability to perform effective testing is compromised
Solution Approach 1:
By introducing double-sided testing capability, the patent overcomes the limitations of thin wafer thickness. The ability to access redistribution structures from both sides enables effective electrical testing even in thinned wafers, maintaining testing reliability while achieving miniaturization.
Solution Approach 2:
The patent performs electrical testing of vias and redistribution structures before wafer singulation and packaging. This preliminary action allows defective chips to be identified and sorted out early, preventing costly rework later in the manufacturing process and maintaining testing effectiveness despite reduced wafer thickness.
3Measurement precision
If double-sided testing is implemented, then comprehensive evaluation of via functionality is achieved, but the testing apparatus complexity increases
Solution Approach 1:
The testing apparatus is designed to accommodate double-sided testing by incorporating probes and positioning mechanisms that can access both the front and rear redistribution structures. This multi-functional design enables comprehensive via functionality evaluation while managing apparatus complexity through integrated test structures.
4Ease of operation
If single-sided testing is used, then the testing process is straightforward, but defective chips cannot be identified before packaging
Solution Approach 1:
The patent implements preliminary electrical testing of vias and redistribution structures before wafer singulation and packaging. This early detection of defective chips allows them to be identified and separated from good chips, preventing waste of functional chips and reducing assembly costs by avoiding packaging of defective units.
Solution Approach 2:
The double-sided testing system provides feedback about the electrical functionality of vias and the quality of rear-side processing. This feedback mechanism enables real-time identification of defective chips and allows for process adjustments, reducing defective chip waste while maintaining operational simplicity through automated testing sequences.
Data Source
AI summary
A method for testing a semiconductor wafer comprises providing a semiconductor wafer. The semiconductor wafer comprises a protruding annular rim, a first redistribution structure disposed on the front side of the semiconductor wafer, a second redistribution structure disposed on the rear side of the semiconductor wafer within the protruding annular rim and a plurality of vias extending from the front side to the rear side. A first probe is contacted to the first redistribution structure on the front side and a second probe is contacted to the second redistribution structure on the rear side. The first probe is in contact with the first redistribution structure and the second probe is in contact with the second redistribution structure at the same time.