Digital PLL Linear Prediction for Spur and Jitter Suppression

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Solution Overview

Problem

Existing digital phase-locked loops (DPLLs) suffer from spurious energy introduction due to time-to-digital converter gain error, non-linearity, and phase error, leading to undesirable periodic tones and increased jitter, which can cause mixing of unwanted signals and emission mask violations.

Innovation Solution

A linear prediction technique is employed to determine the location of spurious content in DPLLs using an all-zero filter with P weights corresponding to P zeros at frequencies of P spurs, suppressing these spurs without increasing the noise floor, and adapting to different loop configurations and environmental changes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional digital phase-locked loop components (time-to-digital converter, fractional divider, phase accumulator) are used, then clock signal generation is achieved, but spurious energy and periodic tones are introduced

Engineering Contradiction:
Improveclock signal qualityVSAvoidspurious energy
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent applies linear prediction filtering to convert the harmful spurious energy into beneficial signal cancellation. The filter predicts and subtracts the periodic tones from the clock signal, transforming the harmful interference into a cleaned clock output. This resolves the contradiction by maintaining reliable clock generation while eliminating spurious energy through active cancellation rather than passive filtering.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The linear prediction filter acts as an intermediary component between the time-to-digital converter and the clock output. It processes the intermediate signal to remove spurious content before final output, serving as a mediator that preserves the functionality of existing DPLL components while eliminating their harmful effects. This allows the system to maintain clock generation reliability without directly modifying the core DPLL architecture.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Object-generated harmful factors

If filtering techniques are applied to suppress spurs, then spurious tones are reduced, but system complexity increases

Engineering Contradiction:
Improvespurious tonesVSAvoidfilter complexity
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The patent uses parameter-based linear prediction filtering where the filter coefficients are determined by analyzing the spectral characteristics of the spurious tones. By changing the filter parameters (coefficients) based on the specific spur frequencies present, the system achieves effective suppression without requiring complex adaptive structures. This resolves the contradiction by using simple filter architecture with adjustable parameters rather than complex adaptive filtering algorithms.

Inventive Principle:
Principle #35Parameter changes

3Object-generated harmful factors

If traditional spur suppression methods are used, then some spurs are reduced, but noise floor increases

Engineering Contradiction:
Improvespur amplitudeVSAvoidnoise floor
Core Design Contradiction:
Object-generated harmful factorsVSManufacturing precision

Solution Approach 1:

The linear prediction filter selectively cancels only the spurious tones while preserving the legitimate clock signal and noise floor. By predicting and subtracting only the periodic components identified through spectral analysis, the method reduces spur amplitude without amplifying or adding noise. This resolves the contradiction by achieving spur suppression through precise spectral targeting rather than broad-spectrum filtering that would affect the noise floor.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS20250211241A1Linear prediction to suppress spurs in a digital phase-locked loop
Publication Date: 2025.06.26 SKYWORKS SOLUTIONS INC
  • US20250211241A1 patent drawing
  • US20250211241A1 patent drawing
  • US20250211241A1 patent drawing

AI summary

A technique uses linear prediction to determine the location of spurious content in a digital phase-locked loop and suppresses the spurious content from propagating to the clock output. In at least one embodiment, the technique implements an iterative (e.g., recursive) computation.