DPLL DCO Supply Adjustment for Temperature and Voltage Drift
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Digital phase locked loops (DPLLs) face challenges in maintaining phase lock due to temperature and power supply voltage drift, leading to increased power consumption and silicon area, as they require a wider range of fine control codes to compensate for these changes, which can result in the fine control code running out of range.
Innovation Solution
A system and method that adjusts the power supply level to the digitally controlled oscillator (DCO) using a voltage adjustment unit, monitored by a logic unit, to keep the fine control code near the middle of its range, reducing the need for a wider range of fine control codes and thereby minimizing power consumption and silicon area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a wider range of fine control code is designed to compensate for temperature and power supply voltage drift, then the DPLL can maintain phase lock under varying conditions, but the DCO size increases resulting in higher power consumption and larger silicon area
Solution Approach 1:
The patent dynamically adjusts the power supply voltage to the DCO based on detected drift conditions (temperature changes, power supply variations). By changing the voltage parameter, the system compensates for drift effects without requiring a wider fine control code range, thus maintaining phase lock while keeping the DCO size and power consumption low.
Solution Approach 2:
The patent implements a feedback mechanism where the system detects phase errors and drift conditions, then adjusts the power supply voltage to the DCO accordingly. This closed-loop control allows the DPLL to maintain phase lock under varying conditions without increasing the fine control code range, resolving the contradiction between reliability and power consumption.
2Reliability
If a wider range of fine control code is designed to compensate for temperature and power supply voltage drift, then the DPLL can maintain phase lock under varying conditions, but the silicon area increases
Solution Approach 1:
The patent changes the power supply voltage parameter to compensate for drift, eliminating the need for a wider fine control code range. This approach maintains phase lock reliability while keeping the DCO and associated logic units compact, thus reducing silicon area.
Solution Approach 2:
The feedback mechanism detects drift conditions and adjusts the power supply voltage accordingly, allowing the system to maintain phase lock without increasing the fine control code width. This reduces the silicon area required for the DCO and control logic while ensuring reliable operation under varying conditions.
3Reliability
If a wider range of fine control code is designed to compensate for temperature and power supply voltage drift, then the DPLL can maintain phase lock under varying conditions, but the quantization noise of the DCO increases
Solution Approach 1:
The patent adjusts the power supply voltage to compensate for drift, which maintains phase lock without requiring a wider fine control code range. By avoiding the need for additional fine control bits, the system prevents increase in quantization noise while maintaining reliability.
4Adaptability or versatility
If the fine control code range is increased to compensate for drift, then temperature and power supply voltage variations can be handled, but the logic unit requires more logic to generate more bits for the fine control code
Solution Approach 1:
The patent changes the power supply voltage parameter to provide drift compensation capability, eliminating the need for a wider fine control code. This approach maintains adaptability to temperature and voltage variations while keeping the logic unit simple, as it only needs to generate the original fine control code bits without additional bits for expanded range.
Solution Approach 2:
The feedback mechanism provides drift compensation by adjusting the power supply voltage based on detected conditions. This approach achieves adaptability without increasing the fine control code width, thereby maintaining simple logic unit design while handling temperature and power supply variations.
Data Source
AI summary
Described herein are apparatus, system, and method for controlling temperature drift and/or voltage supply drift in a digital phase locked loop (DPLL). The apparatus comprises a DPLL including a digital filter to generate a fine code for controlling a frequency of an output signal of a digital controlled oscillator (DCO) of the DPLL; a logic unit to monitor the fine code and to generate a compensation signal based on the fine code; and a voltage adjustment unit to update a power supply level to the DCO based on the compensation signal, wherein the updated power supply level to cause the digital filter to generate the fine code near the middle of an entire range of the fine code across various temperatures, and wherein the digital filter to generate the fine code near the middle of the entire range across power supply drift.


