Digital PLL TDC Calibration for Stable High-Frequency Clock Locking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Digital phase locked loop (DPLL) circuits face challenges in achieving accurate phase locking and reducing noise in high-frequency clock signals, particularly due to metastability and variations in time-to-digital converter (TDC) measurements, which affect their performance and integration in compact, low-power digital circuits for mobile devices.
Innovation Solution
The implementation of multiple digital feedback loops with a time-to-digital converter (TDC) and a digitally controlled oscillator (DCO) that includes calibration circuits to improve TDC accuracy, reduce noise, and mitigate metastability, along with a supervisor circuit to adjust delays and sampling, ensuring phase locking and frequency stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Difficulty of detecting and measuring
If a time-to-digital converter (TDC) is used to measure phase difference in a digital phase locked loop, then phase detection capability is improved, but measurement precision deteriorates due to metastability and TDC variations
Solution Approach 1:
The patent employs a feedback mechanism where the measured phase difference is fed back to adjust the DCO frequency, creating a closed-loop system that continuously corrects phase errors. This feedback loop compensates for TDC measurement variations and metastability effects, improving overall measurement precision while maintaining phase detection capability.
Solution Approach 2:
The patent implements preliminary calibration of the TDC module before normal operation. By pre-characterizing and storing correction values for the TDC, the system compensates for inherent TDC variations and metastability issues before they affect measurement accuracy, thereby improving measurement precision without sacrificing phase detection capability.
2Reliability
If multiple digital feedback loops are implemented to improve phase locking accuracy, then phase locking performance is improved, but device complexity increases
Solution Approach 1:
The patent divides the phase locking function into multiple independent feedback loops, each handling specific aspects of phase correction. This segmentation allows each loop to be optimized for its specific function while working together to achieve overall phase locking accuracy, managing complexity through functional decomposition.
Solution Approach 2:
The patent designs the feedback loops to share common components such as the TDC module and DCO, allowing these components to serve multiple functions across different loops. This multi-functionality reduces the overall device complexity while maintaining multiple feedback paths for improved phase locking accuracy.
3Area of stationary object
If TDC module size is reduced for compact integration, then device compactness is improved, but measurement precision deteriorates
Solution Approach 1:
The patent changes the operational parameters of the reduced-size TDC module through calibration and correction techniques. By adjusting measurement parameters and applying digital correction algorithms, the system maintains measurement precision despite the physical reduction in TDC module size, enabling compact integration without sacrificing accuracy.
Data Source
AI summary
Designs of devices having digital phase locked loop (DPLL) circuits that include multiple digital feedback loops to generate high frequency clock signals by a digitally controlled oscillator (DCO). A time-to-digital converter (TDC) module is provided in such a DPLL circuit to receive an input reference clock signal and a first feedback clock signal from a first digital feedback loop and produces a digital TDC output indicative of a first phase error caused by a difference in time between the input reference clock signal and the first feedback clock signal. A second digital feedback loop is provided to generate a second digital feedback signal indicative of a second phase error caused by a difference in frequency between a desired clock signal and a generated clock signal generated by the DCO. The first and second digital feedback loops are coupled to the DCO to generate the high frequency clock signals.