Selective DQ Clock Gating for Memory Command Synchronization
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Solution Overview
Problem
High-frequency clock signals in memory devices pose challenges for synchronizing command and clock signals, leading to potential errors in data read and write operations, and existing synchronization methods consume additional power, which is a concern for power efficiency.
Innovation Solution
The implementation of a delay locked loop clock signal system that selectively transmits the clock signal based on read and write commands, using logic gates and flip-flops to automatically synchronize and de-synchronize the clock enable signal, reducing power consumption by controlling when the clock signal is transmitted to the DQ system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If additional circuitry is provided for command and clock synchronization, then synchronization accuracy is improved, but power consumption increases
Solution Approach 1:
The patent extracts the clock signal transmission to the DQ system selectively, enabling it only when read commands are active. By removing continuous clock transmission and replacing it with conditional transmission controlled by logic gates, the design achieves synchronization accuracy only when needed, thereby reducing power consumption during non-read operations.
Solution Approach 2:
The patent implements periodic activation of the clock signal based on read command activity. The clock signal is transmitted periodically only during read operations rather than continuously, allowing the system to maintain synchronization capability when required while minimizing power consumption during idle or write-only periods.
2Productivity
If clock signal frequency is increased to improve data rate, then productivity is improved, but synchronization difficulty increases
Solution Approach 1:
The patent introduces logic gates as intermediary components between the clock signal source and the DQ system. These logic gates act as mediators that conditionally gate the high-frequency clock signal based on read command activity, simplifying the synchronization control by decoupling the high-frequency clock generation from continuous DQ system clocking.
Data Source
AI summary
An apparatus may include a delay line that receives a command signal and provides a delayed command signal. The apparatus may include an edge starter that provides a clock enable signal responsive, at least in part, to a change in level of the command signal. A gate circuit of the apparatus may provide a shift clock signal responsive, at least in part, to the clock enable signal. The apparatus may also include a shifter that captures and shifts the delay command signal responsive, at least in part, to the shift clock signal.