DQ Terminal PRBS Variation Through Selectable LFSR Latches
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Solution Overview
Problem
Existing memory devices face a need to increase the variation of pseudo-random bit streams (PRBS) between different data terminals to enhance the difference between bit streams, while minimizing additional circuitry and mode register settings.
Innovation Solution
Implementing a memory device with a linear feedback shift register (LFSR) circuit and a multiplexer system that allows each data terminal to be coupled to a specific latch, controlled by unique LFSR variation settings, ensuring each terminal receives a distinct bit stream, thereby increasing variability without requiring extensive additional circuits or mode register settings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single LFSR circuit is used to generate PRBS for multiple data terminals, then circuit complexity is reduced, but the variation between bit streams on different data terminals is insufficient
Solution Approach 1:
The patent divides the LFSR circuit into multiple segments or instances, with each data terminal having its own LFSR instance or segment. This segmentation allows each terminal to generate independent PRBS sequences with sufficient variation while keeping each individual LFSR segment relatively simple in structure.
Solution Approach 2:
The patent applies different characteristics or configurations to different parts of the system - each data terminal receives a PRBS sequence with locally optimized variation properties. This is achieved through different seed values, different LFSR tap configurations, or different selection combinations for each terminal, ensuring local quality of PRBS variation without requiring complete system redesign.
2Adaptability or versatility
If multiple independent LFSR circuits are used for each data terminal, then PRBS variation between terminals is maximized, but device complexity and resource overhead increase
Solution Approach 1:
The patent merges multiple LFSR circuits into a single shared LFSR structure that generates PRBS for multiple data terminals simultaneously. By using a single LFSR with multiple output taps or by time-multiplexing the LFSR output to different terminals, the patent achieves sufficient PRBS variation while sharing the core circuit resources, thereby reducing overall device complexity.
Solution Approach 2:
The patent designs a universal LFSR circuit that can serve multiple data terminals through different configuration settings. A single LFSR circuit is configured to provide PRBS sequences to multiple terminals by changing seed values, tap selections, or output combinations, making the circuit multi-functional and reducing the need for separate dedicated LFSRs for each terminal.
3Adaptability or versatility
If extensive additional circuits and mode register settings are implemented, then PRBS variation between terminals is improved, but space overhead and resource consumption increase
Solution Approach 1:
The patent employs dynamic configuration of the LFSR circuit where seed values, tap selections, or output combinations can be changed during operation or reconfiguration. This dynamic approach allows the same physical circuit to provide different PRBS sequences to different terminals or under different conditions, achieving high adaptability without requiring additional static circuitry for each configuration.
Solution Approach 2:
The patent achieves PRBS variation by changing parameters of the existing LFSR circuit such as seed values, feedback tap positions, or output selection combinations. By modifying these parameters rather than adding physical circuit elements, the patent achieves diverse PRBS sequences for multiple terminals with minimal space overhead, utilizing parameter space instead of physical space.
Data Source
AI summary
A memory device includes a pseudo-random bit stream (PRBS) generator circuit with a linear feedback shift register (LFSR) which has a number of latches. The data terminals of the memory are associated with a LFSR variation circuit which selects one of the latches and couples the selected latch to the associated data terminal. By varying settings such as which latch each of the DQ terminals are coupled to, the sequence of bits of the PRBS may be varied between the data terminals.