DQS-Domain Data Routing to Bank Logic With Relaxed Timing
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Solution Overview
Problem
Conventional memory devices face challenges with tight timing requirements and misalignment issues during data routing from the DQS domain to the clock domain, leading to potential operational inefficiencies and alignment issues.
Innovation Solution
The data routing is performed entirely within the DQS domain until it reaches the bank logic, using a bank address shifted into the DQS domain and decoded into a sample signal to direct data through a multiplexer, maintaining timing tolerance and alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data routing is performed from DQS domain to clock domain, then data can be routed to bank logic, but timing requirements become tight and misalignment issues occur
Solution Approach 1:
The patent introduces a bank address shift register as an intermediary component that temporarily stores the bank address in the DQS domain before routing. This register acts as a mediator between the DQS domain (where data arrives) and the clock domain (where bank logic operates), allowing the address to be shifted into synchronization with the data strobe signal. This intermediary mechanism extends the timing window and prevents misalignment issues that would otherwise occur during direct domain crossing.
2Reliability
If bank address is shifted into DQS domain, then timing window tolerance is extended, but device complexity increases
Solution Approach 1:
The bank address shift register serves multiple functions: it stores the bank address, shifts the address into synchronization with the DQS signal, and provides the shifted address to the multiplexer for data routing. By making this single component multi-functional, the patent achieves timing window extension without proportionally increasing device complexity. The same register that handles address storage also performs the timing synchronization and routing control functions.
Data Source
AI summary
A memory device receives a bank address in a clock domain and data in a data strobe (DQS) domain. The bank address is shifted into the DQS domain and the shifted bank address is used to route the data to a bank group logic region. In this way, the data remains in the DQS domain until it enters the bank group logic region. This may allow for relaxed timing requirements compared to shifting the data into the clock domain before routing it to the bank group logic region.