Drain Pad Cavity Layout for Low-Capacitance Wire-Bonded Semiconductors
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Solution Overview
Problem
Existing semiconductor devices face challenges in securing strength for wire bonding while reducing parasitic capacitance due to the formation of cavities directly below bonding portions of wires.
Innovation Solution
A semiconductor device design that includes a cavity formed in the substrate directly below the drain pad, but not directly below the bonding portion of the wire, thereby reducing parasitic capacitance and maintaining structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a cavity is formed directly below the bonding portion of the wire to reduce parasitic capacitance, then the parasitic capacitance is reduced, but the strength for bearing wire bonding impact is insufficient
Solution Approach 1:
The cavity is positioned locally beneath the drain pad rather than directly under the wire bonding portion, creating a localized low-parasitic-capacitance region where needed while preserving structural integrity at the bonding location. This spatial differentiation of cavity placement resolves the contradiction by applying the beneficial effect (parasitic capacitance reduction) only where electrically critical, while maintaining mechanical strength where structurally critical.
2Object-affected harmful factors
If the drain pad area is increased to reduce parasitic capacitance, then the parasitic capacitance is reduced, but the device area increases
Solution Approach 1:
Instead of reducing parasitic capacitance by increasing the drain pad area in the planar dimension, the invention introduces a vertical dimension by forming a cavity beneath the pad. This three-dimensional approach reduces the effective capacitance area without increasing the footprint, effectively decoupling capacitance reduction from area expansion.
Data Source
AI summary
An epitaxial layer (2) is formed on a substrate (1). A field effect transistor (3) is formed on the epitaxial layer (2). A drain pad (8) is formed on the epitaxial layer (2). The drain pad (8) is connected to a drain electrode (5) of the field effect transistor (3). A back surface electrode (13) is formed on a back surface of the substrate (1) and connected to a source electrode (6) of the field effect transistor (3). A wire (16) is bonded to the drain pad (8). A cavity (17) is formed in the substrate (1) directly below the drain pad (8). The cavity (17) is not formed directly below a bonding portion of the wire (16).