Semiconductor Assembly Layout for High-Density DRAM Interconnection
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Solution Overview
Problem
The challenge of increasing the degree of integration in dynamic random access memory (DRAM) to meet growing memory demands and bridge the gap between memory demand and capacity is addressed by developing a semiconductor structure with enhanced packaging density.
Innovation Solution
A semiconductor structure is designed with specific connection pads and memory cell regions, incorporating interconnection and redistribution layers to facilitate flexible arrangement of semiconductor devices, reducing the memory cell region area and enhancing packaging efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If packaging density is increased to obtain higher memory capacity, then memory capacity is improved, but manufacturing complexity increases
Solution Approach 1:
The memory structure is divided into multiple semiconductor devices (first semiconductor device, second semiconductor device) arranged in the first direction, with separate connection pads and connection portions for each device. This segmentation allows independent optimization of each device while achieving high overall capacity through parallel arrangement.
Solution Approach 2:
Connection pads are distributed on both the first surface and second surface of the substrate, utilizing the third dimension (vertical stacking) to increase connection density. The first connection pad and fourth connection pad on the first surface connect to the first semiconductor device, while the third connection pad and fifth connection pad on the second surface connect to the second semiconductor device, effectively using vertical space to reduce manufacturing complexity.
2Area of stationary object
If memory cell region area is reduced to enhance packaging efficiency, then packaging density is improved, but interconnection complexity increases
Solution Approach 1:
The first connection portion connects both the first semiconductor device and second semiconductor device to the third connection pad, merging multiple connection functions into a single connection structure. This reduces the number of separate interconnections needed and simplifies the overall interconnection complexity while maintaining compact memory cell region area.
Solution Approach 2:
The first connection portion serves multiple functions: it connects to at least one of the first semiconductor device or second semiconductor device, and simultaneously connects to the third connection pad. This multi-functional connection structure reduces interconnection complexity by eliminating the need for separate dedicated connection paths for each device.
3Productivity
If connection pads are arranged on both surfaces to increase integration, then degree of integration is improved, but manufacturing difficulty increases
Solution Approach 1:
Connection pads are strategically placed on both the first surface and second surface of the substrate to utilize vertical space. The first connection pad and fourth connection pad are disposed on the first surface, while the third connection pad and fifth connection pad are disposed on the second surface, effectively using the third dimension to increase integration without significantly complicating manufacturing processes.
Solution Approach 2:
The connection pad arrangement is segmented by surface: pads on the first surface (first connection pad, fourth connection pad) serve different devices than pads on the second surface (third connection pad, fifth connection pad). This segmentation allows for standardized manufacturing processes on each surface while achieving high overall integration through the combined multi-surface architecture.
Data Source
AI summary
A semiconductor structure includes: a first surface and a second surface that are opposite to each other; a first and a second connection pads that are disposed on the first surface, and a third connection pad, a fourth connection pad, and a fifth connection pad that are disposed on the second surface; a memory cell region disposed between the first and the second surfaces, including a first and a second semiconductor devices that are arranged in a first direction, and a first connection portion, where the first connection pad and the fourth connection pad are connected to the first semiconductor device, the second connection pad and the fifth connection pad are connected to the second semiconductor device, the first connection portion is connected to at least one of the first semiconductor device and the second semiconductor device, and the first connection portion is connected to the third connection pad.