DRAM Bank Section Write Scheme for Faster Fault Testing
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Solution Overview
Problem
The existing methods for testing Dynamic Random Access Memory (DRAM) chips are inefficient due to the time-consuming process of detecting and writing data to faulty storage units, leading to prolonged testing times and increased costs, especially when using a normal write mode or general compression writing mode.
Innovation Solution
A memory system with a bank configuration that includes multiple sections of word lines, bit lines, and storage units, where a control signal activates word lines and adjusts bit line voltages, including complementary bit lines from adjacent sections, to enable rapid detection and correction of faulty units through a compression writing mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If normal write mode or general compression writing mode is used for testing DRAM chips, then the testing process can be completed, but the test time is prolonged and test costs increase due to time-consuming detection and writing to faulty storage units
Solution Approach 1:
The memory bank is divided into multiple sections, with each section containing multiple word lines and bit lines. This segmentation allows parallel testing operations across different sections, significantly reducing overall test time while maintaining comprehensive coverage of the memory structure.
Solution Approach 2:
The patent combines the detection and writing operations into a single integrated process. By merging these previously separate sequential operations, the system eliminates the time-consuming step of detecting faulty units and then writing to them separately, thereby reducing test time and improving efficiency.
2Reliability
If traditional testing methods are used to detect and repair faulty memory cells, then memory reliability can be ensured, but the testing process becomes complex and time-consuming
Solution Approach 1:
The patent implements preliminary action by pre-configuring the memory structure with specific word lines and bit lines that enable direct access to faulty cells. The control circuit is pre-designed to automatically identify and write to faulty units without requiring complex real-time detection algorithms, thereby simplifying the testing process while ensuring reliability.
3Measurement precision
If comprehensive testing of all memory cells is performed, then detection accuracy is improved, but testing time and operational complexity increase
Solution Approach 1:
The patent employs dynamic control of word lines and bit lines through control circuits that can rapidly switch between different testing configurations. This dynamic approach allows the system to adaptively focus testing resources on areas where defects are detected, maintaining high detection accuracy while reducing overall testing time by avoiding exhaustive testing of all cells uniformly.
Data Source
AI summary
A memory includes a bank, the bank includes a plurality of sections, each of the plurality of section includes a plurality of word lines, a plurality of bit lines, and a plurality of storage units arranged in an array, and each of the plurality of storage units is connected to one of the plurality of word lines and one of the plurality of bit lines; the bank is configured to: in a preset mode, in response to a control signal, activate each of a plurality of word lines in at least one target section of the bank, pull up or pull down a level of each of a plurality of bit lines in the target section, and pull a complementary bit line of each of the plurality of bit lines in the target section to a level opposite to a level of the plurality of bit lines.