DRAM Bit Line Layout for Uniform Sense Amplifier Timing
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Solution Overview
Problem
Existing memory devices face challenges in efficiently integrating memory cells and improving storage density, particularly in dynamic random access memory (DRAM) devices with vertical transistors, where the coupling between memory cell arrays and sense circuits is not optimized for efficient data transfer and storage.
Innovation Solution
The memory device employs a configuration with alternating arrangements of sub-arrays and sense amplifiers, utilizing shared bit lines and complementary bit lines coupled to sense circuits through balanced current paths, enhancing integration and storage density by using vertical transistors with gate-all-around structures and oxide semiconductors like In-Ga-Zn oxide for improved control and capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bit lines are connected to sense circuits with varying path lengths, then device complexity is reduced, but signal reception timing differences cause reliability issues
Solution Approach 1:
The memory device is divided into multiple banks, with each bank containing sense amplifiers and bit lines arranged in a specific pattern. This segmentation allows each bank to independently maintain uniform current path lengths while the overall device achieves high integration density.
Solution Approach 2:
Within each bank, sense amplifiers are positioned asymmetrically relative to bit lines to compensate for path length variations. The sense amplifiers are strategically placed at different distances from bit lines to equalize the total current path lengths, creating a balanced electrical characteristic despite physical asymmetry.
2Reliability
If sense amplifiers are arranged to equalize current path lengths, then reliability improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies different arrangement strategies to different regions within banks. Sense amplifiers in adjacent banks may have different positioning configurations, allowing each local region to achieve path length uniformity through methods best suited to its specific layout constraints and manufacturing capabilities.
3Productivity
If bit lines are commonly connected across multiple banks, then productivity increases, but signal interference risks increase
Solution Approach 1:
Isolation structures are introduced as intermediary elements between adjacent banks that share common bit lines. These structures act as electrical barriers or buffers that prevent signal interference and crosstalk between banks while maintaining the electrical connectivity needed for common bit line operation.
Data Source
AI summary
A memory device includes, a memory cell array including first to fourth sub-arrays, a first bit line coupled to the first sub-array and the second sub-array, a second bit line arranged side by side with the first bit line in a first direction and coupled to the third sub-array and the fourth sub-array, a third bit line arranged at a position different from the first bit line in a second direction and coupled to at least the second sub-array and the third sub-array, a fourth bit line arranged side by side with the third bit line in the first direction and coupled to the fourth sub-array, a first circuit electrically coupled to the first bit line and the second bit line, and a second circuit electrically coupled to the third bit line and the fourth bit line.