DRAM Capacitor Hole Patterning for Uniform High-Aspect-Ratio Etching
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Solution Overview
Problem
The increasing integration level and reduced transverse dimension of Dynamic Random Access Memory (DRAM) components lead to manufacturing difficulties, including interconnection issues, insufficient etching, and size and depth differences in capacitor tubes during etching processes.
Innovation Solution
A method involving the formation of a stack with sacrificial and supporting layers, followed by the creation of etching patterns in mask layers to form capacitor holes, ensuring planarization and uniformity to avoid impurity residues and material accumulation, thereby achieving consistent depths and sizes of capacitor holes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the integration level is continuously improved and transverse dimension is reduced, then the capacitor has higher aspect ratio and higher density, but the manufacturing process becomes increasingly difficult with interconnection issues, insufficient etching, and size/depth differences in capacitor tubes
Solution Approach 1:
The patent divides the single etching process into multiple sequential etching steps (first etching, second etching, third etching) with different etching conditions and parameters. Each etching step targets specific depth ranges and addresses different aspects of the capacitor hole formation, thereby achieving uniform etching results while managing process complexity through systematic breakdown of the manufacturing process
Solution Approach 2:
The patent applies preliminary actions by performing surface treatment and planarization steps before the etching process, and by using specific etching conditions in earlier steps to prepare the substrate for subsequent etching steps. This preliminary preparation ensures that the etching process proceeds uniformly and prevents interconnection issues and insufficient etching
2Area of stationary object
If the transverse dimension is reduced to achieve higher integration, then the capacitor aspect ratio increases, but etching uniformity deteriorates with size difference and depth difference of capacitor tubes
Solution Approach 1:
The patent employs dynamic adjustment of etching parameters across multiple sequential etching steps. Each etching step uses different etching conditions (etching gas composition, power, pressure, temperature) optimized for specific depth ranges. This dynamic parameter adjustment ensures uniform etching depth and size across capacitors with high aspect ratios, preventing size and depth differences
Solution Approach 2:
The patent systematically changes etching parameters between different etching steps, including etching gas composition (switching between CF4, SF6, C4F8), power levels, pressure, and temperature. These parameter changes are specifically designed to achieve uniform etching results for high aspect ratio capacitors, addressing the depth uniformity issue while maintaining reduced transverse dimensions
Data Source
AI summary
A method for manufacturing a semiconductor structure includes: a first mask layer is formed on a dielectric layer, in which a first etching hole extending along a first direction parallel to the dielectric layer is formed in the first mask layer; a side of the first mask layer away from the dielectric layer is planarized; a second mask layer is formed on the first mask layer, in which a second etching hole extending along a second direction parallel to the dielectric layer is formed in the second mask layer, the first etching hole and the second etching hole constitute an etching hole; and the dielectric layer is etched along the etching hole to form the capacitor hole.