DRAM Capacitor Electrode Structure to Prevent Voids and Seams

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Solution Overview

Problem

As integrated circuit devices downscale, the formation of capacitor structures with high dielectric constants is hindered by voids and seams in bottom electrodes, leading to deteriorated electrical performance in DRAM devices.

Innovation Solution

The integration of a bottom electrode with a conductive capping layer of niobium nitride and a dielectric layer of hafnium oxide in a tetragonal crystal phase, supported by a structure that prevents voids and seams, enhances the capacitance while maintaining electrical integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If capacitor structures are downscaled to increase integration density, then device capacity increases, but voids and seams form in bottom electrodes leading to deteriorated electrical performance

Engineering Contradiction:
Improveintegration densityVSAvoidelectrical performance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent changes the material parameter of the bottom electrode from conventional materials to niobium nitride, which has superior fill properties that prevent void and seam formation during downscaling. This material parameter change enables maintaining electrical performance while achieving higher integration density through continued capacitor miniaturization.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent employs a composite structure consisting of niobium nitride base electrode layer combined with a conductive capping layer. This composite material approach leverages the fill capabilities of niobium nitride and the conductivity of the capping layer to eliminate voids and seams while ensuring electrical integrity in downscaled capacitor structures.

Inventive Principle:
Principle #40Composite materials

2Reliability

If high dielectric constant materials are used to increase capacitance, then capacitor performance improves, but manufacturing complexity increases

Engineering Contradiction:
ImprovecapacitanceVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent utilizes hafnium oxide in its tetragonal crystal phase, which possesses inherently high dielectric constant properties. This material parameter enables achieving high capacitance values without requiring complex multi-layer dielectric stacks or additional processing steps, thereby maintaining manufacturing simplicity while improving capacitor performance.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution allows for the formation of capacitor structures with high dielectric constants and reduced voids or seams in bottom electrodes, improving the electrical performance and reliability of DRAM devices.

Implementation Method 1

a conductive capping layer including niobium nitride and between a sidewall of the base electrode layer and the dielectric layer, and also between a top surface of the base electrode layer and the dielectric layer

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 2

a portion of the dielectric layer in contact with the base electrode layer includes hafnium oxide having a tetragonal crystal phase

Methodology Applied
Scientific EffectCrystallisation: Crystallisation

Implementation Method 3

forming a dielectric layer on the bottom electrode and the supporter

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Data Source

PatentUS11929393B2Integrated circuit devices and methods of manufacturing the same
Publication Date: 2024.03.12 SAMSUNG ELECTRONICS CO LTD
  • US11929393B2 patent drawing
  • US11929393B2 patent drawing
  • US11929393B2 patent drawing

AI summary

An integrated circuit device includes a capacitor structure, wherein the capacitor structure includes: a bottom electrode over a substrate; a supporter on a sidewall of the bottom electrode; a dielectric layer on the bottom electrode and the supporter; and a top electrode on the dielectric layer and covering the bottom electrode. The bottom electrode comprises: a base electrode layer over the substrate and extending in a first direction that is perpendicular to a top surface of the substrate, and a conductive capping layer including niobium nitride that is between a sidewall of the base electrode layer and the dielectric layer, and also between a top surface of the base electrode layer and the dielectric layer.