Phase Adjusting Circuit Using Duty-Cycle Feedback for DRAM Clocks
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Solution Overview
Problem
The phase skew between clock paths in a Dynamic Random Access Memory (DRAM) due to mismatch and noise affects the performance of the memory, as the four clock paths with 90-degree phase differences are not accurately maintained.
Innovation Solution
A phase adjusting circuit comprising a detection circuit, comparison circuit, counter, and adjustment circuit is used to detect phase differences between clock signals, perform duty cycle comparison, count pulses, and adjust the clock signals to ensure a 90-degree phase difference within an allowable error range, thereby correcting phase skew.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If four clock paths are used to achieve 90-degree phase differences, then the memory can support higher data rates and improved performance, but phase skew and noise increase, affecting signal accuracy
Solution Approach 1:
The patent implements a feedback mechanism where the detection circuit continuously monitors phase differences between clock paths and feeds this information to the adjustment circuit. The adjustment circuit then modifies delay parameters to correct phase skew, creating a closed-loop system that maintains accurate 90-degree phase differences despite variations in operating conditions
Solution Approach 2:
The patent replaces physical mechanical alignment methods with electronic phase detection and adjustment mechanisms. Instead of relying on precise physical routing to maintain phase relationships, the system uses detection circuits to measure phase differences and adjustment circuits to electronically correct them, achieving superior phase accuracy
2Ease of manufacture
If phase skew is allowed to vary, then the circuit design becomes simpler and manufacturing is easier, but mismatch and noise increase, degrading memory performance
Solution Approach 1:
The patent implements a self-adjusting system where the phase adjustment circuit automatically detects and corrects its own phase skew without external intervention. The detection circuit monitors the clock paths and provides feedback to the adjustment circuit, enabling the system to self-correct phase errors and maintain signal integrity
Solution Approach 2:
The patent dynamically adjusts delay parameters in the adjustment circuit based on detected phase differences. By changing the delay parameter values in response to measured phase skew, the system maintains accurate phase relationships despite variations in manufacturing tolerances, temperature, or voltage
Data Source
AI summary
A phase adjusting circuit, a delay locking circuit, and a memory are provided. The phase adjusting circuit includes a detection circuit, a comparison circuit, a counter, and an adjustment circuit that are connected in sequence. The detection circuit is configured to detect a phase difference between a first clock signal and a second clock signal to obtain a first detection signal and a second detection signal. The comparison circuit is configured to perform duty cycle comparison of the first detection signal and the second detection signal to obtain a counting indication signal. The counter is configured to count a number of pulses of a preset counting clock signal based on the counting indication signal to obtain a count value. The adjustment circuit is configured to perform phase adjustment of the second clock signal based on the count value, so that the phase difference is a preset value.