DRAM Delay Control Circuit for ECS Timing Under PVT Variation
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Solution Overview
Problem
Current semiconductor technologies fail to guarantee the timing requirements between internally generated command signals in DRAM operations, particularly during Error Check and Scrub (ECS) modes, due to the absence of external clock signals and the influence of process, voltage, and temperature (PVT) variations affecting delay lines.
Innovation Solution
A delay control circuit that performs non-clock-triggered delay processing on initial command signals using a delay circuit connected to a stable voltage generation circuit, ensuring timing compliance through a series of delay sub-circuits and voltage conversion, independent of external clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If non-clock-triggered delay processing is used in ECS mode, then timing requirements between command signals are met, but external clock signals are not required
Solution Approach 1:
The delay control circuit is divided into multiple delay sub-circuits (first delay sub-circuit, second delay sub-circuit, etc.) that can be selectively activated. Each sub-circuit handles a specific portion of the total delay time, allowing the system to meet precise timing requirements while maintaining manageable circuit complexity through modular design.
Solution Approach 2:
The circuit dynamically selects which delay sub-circuits to activate based on the specific timing requirements of different command signal pairs. This dynamic configuration allows the same circuit to adapt to varying timing needs without requiring complex redesign, resolving the contradiction between reliability and complexity.
2Manufacturing precision
If delay lines are used to meet timing requirements, then time intervals between command signals are controlled, but PVT variations affect delay accuracy
Solution Approach 1:
The circuit compensates for PVT variations by adjusting the activation timing and duration of different delay sub-circuits based on detected timing deviations. When PVT changes cause delay drift, the control logic modifies which sub-circuits are activated and for how long, restoring accurate timing without requiring physically larger or more complex delay structures.
Solution Approach 2:
The system incorporates timing detection and feedback mechanisms that monitor the actual time intervals between command signals and compare them against required specifications. Based on this feedback, the control circuit adjusts the delay sub-circuit activation patterns to compensate for PVT-induced timing errors, maintaining manufacturing precision despite environmental variations.
3Adaptability or versatility
If multiple delay sub-circuits are used, then timing flexibility is improved, but circuit complexity increases
Solution Approach 1:
The total delay requirement is segmented into multiple manageable portions handled by individual delay sub-circuits. This segmentation provides timing flexibility as different combinations of sub-circuits can be activated to meet various timing specifications, while the modular nature keeps each individual sub-circuit simple and the overall design manageable.
Solution Approach 2:
The delay control circuit is designed as a universal timing solution that can handle multiple different timing requirements between various command signal pairs (e.g., ACT to RD, RD to WR, WR to PRE) using the same set of delay sub-circuits. This multi-functionality provides adaptability without proportionally increasing complexity, as the same hardware resources serve multiple timing control purposes.
Data Source
AI summary
A delay control circuit includes a delay circuit. The delay circuit is configured to receive an initial command signal, and to perform a non-clock-triggered delay processing on the initial command signal to obtain a target command signal. The initial command signal is generated based on an ECS operation mode, a time interval between the target command signal and the initial command signal meets a preset timing condition, the initial command signal is used for performing a first operation and the target command signal is used for performing a second operation.