DRAM Cell Layout With Diagonal Gate Pairs for Higher Density
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Solution Overview
Problem
In dynamic random access memory (DRAM) cells, a single transistor cannot uniquely address a memory cell due to the need for the gate to be positioned close to one pillar while avoiding current flow through another, leading to increased pitch and reduced density of memory cells per area, which limits the number of cells that can be formed and manufactured from a given wafer size.
Innovation Solution
Implementing a diagonally opposite gate pair configuration, where two transistors with gates positioned on opposite sides of a pillar at different heights control current flow through separate channels, allowing for unique addressability of a single memory cell and increasing the density of memory cells per area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single transistor is used to control current flow to or from the capacitor, then the memory cell structure is simple, but the gate cannot uniquely address a single memory cell due to positioning constraints, leading to increased pitch and reduced density
Solution Approach 1:
The single transistor control function is segmented into two transistors with diagonally opposite gates. Each transistor controls a different channel (first channel and second channel) through which current can flow to or from the capacitor. This segmentation allows unique addressing of the memory cell by controlling current through different paths, resolving the addressing conflict while maintaining compact layout.
Solution Approach 2:
The gate positions are arranged in a diagonal configuration across different spatial dimensions relative to the capacitor. The first gate is positioned to control the first channel, while the second gate is positioned diagonally opposite to control the second channel. This dimensional arrangement enables unique cell addressing without increasing pitch, as the gates exploit different spatial relationships to the capacitor.
2Reliability
If the gate is positioned close to one pillar to enable current flow control, then current control is effective, but the gate cannot avoid current flow through another pillar, preventing unique addressability
Solution Approach 1:
The current control function is segmented into two independent transistor-gate channels. The first gate controls current through the first channel, and the second gate controls current through the second channel. By activating only the appropriate gate for the target memory cell, current flow is precisely controlled to the desired capacitor without unwanted current flow through other cells, enabling unique addressability while maintaining reliable current control.
Solution Approach 2:
Each gate is positioned to exert its controlling influence locally on a specific channel leading to a specific capacitor. The first gate's electric field is localized to control current through the first channel, while the second gate's electric field is localized to control current through the second channel. This local quality of control ensures that when one gate is activated, it affects only its associated channel and capacitor, preventing unintended current flow through other pillars.
3Ease of manufacture
If pitch is increased to accommodate gate positioning constraints, then gate positioning is feasible, but the number of memory cells per area is reduced
Solution Approach 1:
The two transistors are positioned asymmetrically with respect to the capacitor, with gates located at diagonally opposite positions. This asymmetric arrangement allows both gates to be positioned close to the capacitor without requiring increased pitch, as the diagonal configuration efficiently utilizes the available space around the capacitor. The asymmetric positioning enables unique addressing while maintaining compact cell dimensions.
Solution Approach 2:
The gate positions utilize diagonal spatial relationships, effectively using two-dimensional positioning around the capacitor rather than linear positioning along a single axis. This dimensional approach allows four gates (two per capacitor in a shared configuration) to be positioned close to the capacitor without increasing pitch, maximizing the number of cells per unit area while maintaining feasible gate positioning for current control.
Data Source
AI summary
Implementations described herein relate to various structures, integrated assemblies, and memory devices. In some implementations, an integrated assembly includes a pillar having an upper source/drain, a middle source/drain, a lower source/drain, an upper channel between the upper source/drain and the middle source/drain, and a lower channel between the middle source/drain and the lower source/drain. The integrated assembly includes a gate pair that includes a first gate and a second gate. The first gate is positioned on a first side of the pillar at a first height, and the second gate is positioned on a second side of the pillar, that is opposite the first side, at a second height that is different from the first height. The integrated assembly includes a capacitor that is electrically coupled with the upper source/drain. Some implementations include methods of forming the various structures, integrated assemblies, and memory devices.