3D DRAM Word Line Driver Layout Under Memory Blocks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The positioning of word line drivers outside memory blocks in 3D DRAM architectures limits the efficiency and reduces the size of memory chips, creating a bottleneck for improving memory cell density and chip size reduction.
Innovation Solution
Positioning word line drivers under memory blocks, allowing them to overlap partially with the memory blocks, and arranging even- and odd-numbered word lines to different sets of drivers, while bit lines are coupled to separate sense amplifiers, reducing the gap area between memory blocks and maintaining pitch and spacing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If word line drivers are positioned outside memory blocks in 3D DRAM architectures, then the layout is simpler to implement, but the chip size increases and memory cell density decreases
Solution Approach 1:
The patent transitions from a 2D layout where word line drivers are positioned outside memory blocks to a 3D stacked architecture where drivers are integrated underneath memory blocks in the vertical dimension. This dimensional change allows the drivers to overlap with memory blocks in plan view while being separated in the vertical stacking direction, thereby reducing chip area without compromising manufacturability.
Solution Approach 2:
The word line drivers are nested underneath the memory blocks in the vertical stacking direction, with the driver circuit layer positioned below the memory block layer. This nesting arrangement allows the drivers to be contained within the footprint of the memory blocks, reducing the overall chip area while maintaining functional separation through vertical layering.
2Ease of manufacture
If word line drivers are positioned outside memory blocks, then the circuit routing is easier, but the gap area between memory blocks increases reducing efficiency
Solution Approach 1:
The patent resolves the routing complexity by moving the connection path to the vertical dimension through stacked bonding interfaces. Word lines connect to drivers through vertical interconnects at the bonding interface between stacked layers, eliminating the need for long lateral routing paths and reducing gap areas between memory blocks while maintaining routing simplicity through standardized vertical connections.
3Area of moving object
If word line drivers are positioned under memory blocks with overlapping layout, then chip size is reduced, but the manufacturing complexity increases
Solution Approach 1:
The patent segments the memory device into distinct functional layers stacked vertically: memory blocks in one layer and word line drivers in another layer below. This segmentation allows each layer to be optimized independently for its function while the stacking architecture manages the complexity of inter-layer connections through standardized bonding interfaces and vertical interconnect structures.
4Quantity of substance
If even- and odd-numbered word lines are coupled to different sets of drivers, then memory cell density is increased, but the circuit complexity increases
Solution Approach 1:
The word line drivers are segmented into multiple sets (first set and second set) that are spatially separated and independently organized. Each set drives a specific group of word lines (even or odd numbered), allowing parallel operation and increased memory cell density. The segmentation is managed through separate bonding interfaces and interconnect structures that route signals to the appropriate driver sets without creating excessive complexity.
Data Source
AI summary
Methods, devices, and systems for managing layouts of semiconductor structures in memory devices are provided. In one aspect, a memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first memory block, and the second semiconductor structure includes a driver circuit. The first semiconductor structure and the second semiconductor structure are stacked along a first direction. The driver circuit at least partially overlaps with the first memory block in a plan view perpendicular to the first direction.