3D DRAM Gate Connection Layers for Simpler Gate Formation
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Solution Overview
Problem
In existing 3D DRAM technologies, the gate metal layer for connecting gate structures of adjacent transistors in the same layer cannot be formed simultaneously, leading to a complex preparation process.
Innovation Solution
A method involving the formation of active dummy connection layers by removing first semiconductor layers and isolation structures, allowing for the simultaneous formation of gate structures on these layers, which also serve as electron barriers to reduce leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate metal layer is formed to connect gate structures of adjacent transistors in the same layer, then connectivity between gate structures is improved, but the preparation process becomes complex
Solution Approach 1:
The patent applies preliminary action by forming active dummy connection layers before the gate metal layer. These dummy connection layers are prepared in advance to serve as templates or guides for subsequent gate metal layer formation, thereby simplifying the overall preparation process while ensuring reliable connectivity between adjacent gate structures in the same layer.
2Ease of manufacture
If active dummy connection layers are formed by removing first semiconductor layers and isolation structures, then gate structure formation is simplified, but material removal and layer formation steps are added
Solution Approach 1:
The patent merges multiple functions into the active dummy connection layers. These layers simultaneously serve as: (1) structural supports for gate formation, (2) templates for gate metal layer alignment, and (3) isolation barriers between adjacent transistor regions. By combining these functions into a single integrated structure, the patent simplifies gate structure formation despite adding material removal and layer formation steps.
Data Source
AI summary
A method for forming a semiconductor structure includes: a base is provided, the base including a first area and a second area located outside the first area, the first area including stack structures and first isolation structures arranged alternately in a first direction, each stack structure including first semiconductor layers and second semiconductor layers stacked onto one another alternately in a third direction, the first direction being a direction in a plane where the base is located, the third direction intersecting with the plane where the base is located; the first semiconductor layers located in the first area, and the first isolation structures located in the first area and located in projection areas of the first semiconductor layers in the first direction are successively removed, to form active dummy connection layers extending in the first direction; and gate structures are formed on surfaces of the active dummy connection layers.