DRAM Input Control Circuit for Inverted Power-Down Exit Decoding
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Solution Overview
Problem
Dynamic random access memory (DRAM) systems face challenges in decoding command/address signals during power down mode exit due to command/address inversion, leading to incomplete signal recovery and potential system instability.
Innovation Solution
A control circuit comprising an input control module, an input processing module, and a logic decoding module is designed to receive command/address control signals and command/address inversion signals. The circuit generates drive control signals to produce an intermediate command/address signal, enabling successful decoding of the power down mode exit signal even with command/address inversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If command/address inversion is applied to reduce power consumption in power down mode, then power saving is improved, but decoding of power down mode exit signal fails leading to system instability
Solution Approach 1:
The patent introduces an intermediate command/address signal as a mediator between the inverted command/address control signal and the decoding logic. This intermediate signal undergoes conditional inversion based on the inversion control signal, allowing the decoding module to correctly interpret the power down mode exit signal regardless of the inversion state, thus maintaining decoding reliability while preserving power consumption benefits
Solution Approach 2:
The patent dynamically changes the inversion parameter of the command/address signal based on the inversion control signal. When the control circuit is in power down mode, the inversion parameter is adjusted to ensure proper signal interpretation upon exit from power down mode. This parameter change allows the system to maintain reliable decoding while benefiting from power savings during power down operation
2Loss of energy
If command/address inversion is enabled to save power, then power consumption is reduced, but the circuit complexity increases to handle inversion control
Solution Approach 1:
The control circuit is designed with multi-functionality to handle both inverted and non-inverted command/address signals through a single unified architecture. The inversion control signal dynamically configures the circuit behavior, allowing the same hardware to serve multiple purposes (power saving mode and normal mode) without requiring separate dedicated circuits, thus limiting the increase in overall system complexity
Solution Approach 2:
The patent applies preliminary action by pre-configuring the intermediate command/address signal generation logic and inversion control mechanisms before power down mode is entered. The inversion control signal is prepared in advance to ensure that when the power down mode exit signal needs to be decoded, the correct inversion state is already in place, avoiding the need for complex real-time decision-making circuits
Data Source
AI summary
Provided are a control circuit, a control method, and a memory. The control circuit includes: an input control circuit, configured to generate a first drive control signal and a second drive control signal based on a command/address control signal and a command/address inversion signal; an input processing circuit, configured to generate a first intermediate command/address signal based on the first drive control signal and the second drive control signal when the command/address control signal is in an enabled state, that the circuit is in a power down mode being indicated when the command/address control signal is in the enabled state; and a logic decoding circuit, configured to generate a power down mode exit signal in the power down mode based on the command/address inversion signal and the first intermediate command/address signal.