DRAM Circuit with Integrated Processor Control Interface
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Solution Overview
Problem
The integration of processors within DRAM circuits to reduce data transfer with SoC is hindered by complex and expensive interface implementation, particularly due to the need for arbitration control signal transfer, leading to increased system complexity and cost.
Innovation Solution
A DRAM circuit design with integrated processors that allows seamless communication with the SoC using a DDR protocol-compatible access protocol, where the SoC can delegate processing tasks and manage DRAM processors without direct arbitration, utilizing a DRAM processor control interface and refresh control circuit to coordinate memory access and refresh operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If DRAM circuits have integrated processors to reduce data transfer with SoC, then productivity is improved, but device complexity increases due to complex interface implementation
Solution Approach 1:
The DDR interface is designed to serve multiple purposes: it handles both traditional memory access operations and processor control operations. The interface can interpret commands as either memory access requests or processor control requests based on command type, allowing a single interface to manage both DRAM memory banks and integrated processors without requiring separate dedicated interfaces for each function.
2Productivity
If arbitration control signals are transferred between external processor and internal processor, then productivity is improved, but device complexity increases due to complex signal transfer mechanisms
Solution Approach 1:
The arbitration control signals are merged into the existing DDR interface signal set rather than being transmitted through separate dedicated signal paths. The interface combines memory access commands and processor control commands into a unified command structure, allowing arbitration between multiple processors to be managed through the same physical interface used for memory access, thereby eliminating the need for additional arbitration signal wires and reducing overall system complexity.
3Ease of manufacture
If DDR protocol-compatible access protocol is used for SoC access to DRAM, then ease of manufacture is improved, but device complexity increases due to protocol compatibility requirements
Solution Approach 1:
The interface automatically determines whether a received command is a memory access command or a processor control command based on the command structure itself, without requiring external classification or additional control logic. The command interpretation is self-service in nature, where the interface autonomously routes commands to appropriate targets (DRAM memory banks or integrated processors) based on built-in command type detection, simplifying the overall system architecture.
Data Source
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AI summary
The invention relates to a memory circuit comprising: a memory network comprising at least one memory bank (418); a first processor (420); and a processor control interface for receiving instructions for processing data addressed to the first processor from a central processor (P1, P2), the processor control interface being designed to indicate to the central processor when the first processor has finished accessing at least one memory bank of the memory network, said memory banks becoming accessible for the central processor.