DRAM Neuron Processing Circuits for In-Memory Computing

The patent merges processing functionality directly into the memory device by integrating neuron processing elements with DRAM cells. The processing circuits are embedded within the memory structure, allowing computations to occur in-place without requiring separate CPU/GPU processors. This integration eliminates the processor-memory bottleneck and dramatically reduces energy consumption by eliminating the need for extensive data movement between processor and memory.

The memory device performs self-computation through the integrated neuron processing elements. The DRAM cells with embedded processing circuits can execute computational operations autonomously using data stored within the memory array itself, without requiring external processor intervention. This self-service capability enables in-memory computing that reduces dependency on external processing units and their associated energy consumption.

The patent extracts the processing functionality from the traditional CPU/GPU and embeds it directly within the memory structure. By taking out the computational tasks from external processors and placing them inside the memory cells themselves, the system eliminates the need for high-energy data movement while maintaining data access capability. The processing circuits operate directly on data stored in the memory array.

The integrated processing circuits act as intermediaries between data storage and computational operations. Rather than requiring data to be moved from memory to processor and back, the processing circuits serve as an intermediary layer within memory that can perform computations directly on stored data, reducing the energy-intensive data movement steps.

The processing element is segmented into discrete functional components including weight storage circuits, threshold logic circuits, and output circuits that can be independently designed and integrated into the DRAM architecture. This segmentation allows for modular integration of processing functionality without requiring complete redesign of the entire memory system, thereby managing complexity through structured decomposition.

The processing circuits are designed to perform multiple computational functions using the same basic architectural blocks. The neuron processing elements can execute various operations by configuring the weight storage and threshold logic circuits, allowing a single integrated structure to serve multiple processing purposes. This multi-functionality reduces the need for separate dedicated circuits for different operations.

The processing circuits are nested within the DRAM cell structure, with weight storage circuits and threshold logic circuits embedded inside or adjacent to the memory cells. This nested arrangement allows processing functionality to be contained within the memory array without requiring external interference with the DRAM access protocol. The processing elements utilize the existing DRAM physical structure while maintaining separate computational functionality.

The processing circuits are implemented with local characteristics that are optimized for in-memory computation while maintaining compatibility with the overall DRAM architecture. The weight storage and threshold logic circuits are designed with specific local properties that enable computation without interfering with the global DRAM access protocol. Each processing element maintains local independence that prevents propagation of interference across the memory array.