Physical Realisation TRIZ Cases

Zero-free neuron formatting lets DNN tiles skip zero-valued neurons, cutting ineffectual operations to improve speed and energy use.

Asymmetric and per-channel quantization cut neural network compute and memory use while preserving low-precision inference accuracy.

A DMA controller inside the processor core moves tensors from higher-level buffers without frequent CPU reads, cutting bus load and power use.

Dynamic graph partitioning distributes AI inference workloads across CPU, GPU, and VPU to cut overload, idle time, and sync delays.

By moving ADC and DAC into the photonic circuit, this EPIC design frees FPGA control signals and expands CNN computing bandwidth.

A scheduler assigns ANN operations across PE groups to cut idle time, speed multi-model execution, and lower NPU power use.

A shared NPU scheduler sequences or parallelizes multiple ANN models to cut idle time, speed video enhancement, and lower power use.

Integrated optical modulators and attenuators move ADC and DAC into the photonic circuit to raise CNN throughput with lower power.

Quantized fixed-point neural networks and evolutionary training cut memory and compute demands for end-to-end communication systems.

By convolving only non-zero activations with selected weights, this case cuts compute, energy use, and processing time without changing accuracy.

Micro-batch scheduling and layered backward propagation cut compute-node idle time and communication overhead in parallel model training.

Gauge transformation canonicalizes transformer KV cache states for compression, cutting memory bottlenecks without retraining or major accuracy loss.

Lookup tables and exponent-based coefficient selection speed Gelu computation in ASICs while cutting area and energy without losing accuracy.

Latent vectors from weights and input data adjust quantization levels so neural networks keep precision while improving inference efficiency.

Low-rank error compensation helps compressed LLMs recover output accuracy without retraining while keeping latency and compute overhead low.

Dynamic fixed-point adjustment raises equivalence rates so neural networks can skip redundant feature-map calculations and cut power use.

Mixed-bit neural network layers are split across NPU, GPU, and CPU resources to improve inference efficiency without retraining.

Piecewise linear activation and shared post-processing let one IC handle dot products, matrix multiplication, and softmax with lower power.

By transposing gradients and weights, backward convolution reuses optimized forward kernels to cut training delays and memory strain.

A compiler-controlled transposer switches neural data between width-last and channel-last layouts to cut CPU load, bandwidth use, and power.

Variation-tolerant analog NPU embeddings cut data movement and power while preserving software-equivalent accuracy in large neural networks.

Dynamic video memory reconstruction for grouped backward calculations cuts memory occupancy and avoids recalculation overhead in large-model training.

Integrated neuron processing in DRAM cuts processor-memory data movement, boosting throughput and energy efficiency without disrupting access protocols.

Precomputing intermediate kernel parameters lets a neural processor offload convolutions from the CPU, cutting bandwidth demand and power use.

Conditional KPI-based sampling in wireless systems cuts excess traffic and storage while preserving meaningful data for AI model training.

Bit shifting neural network parameters and rescaling quantization simulates low-bit hardware, cutting power use without added hardware complexity.

Tensor data is split into sub-tensors and moved over parallel memory channels to ease bandwidth strain and speed local-to-external transfers.

Latent vectors from weights and input data adjust quantization levels so neural networks keep accuracy while improving inference efficiency.

A DMA engine converts and compresses DNN weights into accelerator-friendly layouts, cutting storage overhead and reformatting cost.

Skipping key embedding in transformer attention blocks cuts training and inference compute while preserving model performance on constrained devices.

A stacked memory die and logic die linked by TSVs cut data movement, lowering latency and power for flexible neural network computing.

Forecasted embeddings let one autoregressive AI model draft and verify tokens in parallel, cutting compute cost and speeding response generation.

Multi-terminal logic gates and configurable connectors cut neural network inference to one clock cycle while minimizing data movement and power.

Line-based depth-first scheduling and H-reuse caching cut memory access and latency for generative AI on edge processors.

Dynamic ML resource scheduling and MIMO adjustment help terminal devices limit overheating while maintaining communication performance.

Moment penalization reshapes weight and hidden-state distributions to cut quantization loss and preserve neural network accuracy on low-bitwidth accelerators.

Clipping activation outliers during transformer quantization narrows fixed-point ranges and helps preserve accuracy on constrained devices.

Binary-tree threshold traversal cuts quantization memory and comparison overhead, enabling wider-bit neural inference with low latency.

Dynamic bus priority control reallocates tensor memory access by core demand, reducing data starvation, latency, and power use.

Metadata flags non-zero activation regions so the neural network engine skips zero-value reads and convolution fetches to cut memory and compute use.

Split server and device models let federated learning aggregate asynchronously, cutting straggler idle time and improving resource use.

Stochastic bitline multiplication, MOMCAP accumulation, and token-based dataflow cut transformer data movement and energy in DRAM.

Model parameters are split across accelerators so each device fetches needed layers, easing memory pressure and reducing training congestion.

Parallel training and loss-based pruning stabilize small neural material networks for fast, high-fidelity rendering with less aliasing.

Partitioned subnetworks use training data and approximated marginal likelihood to refine hyperparameters faster without a validation set.

Dynamic phase and amplitude modulation in one optical ring resonator enables compact multi-dimensional convolution with lower power and less area.

Balancing encoded and raw data in mini-batches cuts image loading and decoding bottlenecks, improving neural network training throughput.

A LUT-based softmax accelerator uses quantized value distribution and offset indexing to cut computation time and data transfer overhead.

Dynamic fusion of adjacent neural network layers cuts on-chip and off-chip I/O access, improving AI chip resource use and runtime.