Logic-Gate Neural Network Circuit for Single-Cycle Inference
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Solution Overview
Problem
Current computing architectures, such as CPUs, GPUs, and FPGAs, struggle to efficiently process large sensor data streams due to the von Neumann bottleneck, limiting computational throughput and energy consumption, and existing neural networks are constrained by their sequential evaluation and high inference time, especially in applications like autonomous vehicles.
Innovation Solution
A digital neural network design using multi-terminal logic gates and logical connectors, implemented on a single chip with CMOS technology, allows for real-time evaluation and inference by configuring logical connector states through integer linear programming, enabling ultra-low-power computing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional neural networks are implemented on CPUs, GPUs, or FPGAs, then computational capability is provided, but the von Neumann bottleneck limits computational throughput and increases energy consumption
Solution Approach 1:
The patent merges the neural network computation and data storage functions into a single integrated circuit. The neural network is implemented using logic gates and logical connectors that are physically embedded within the same chip, eliminating the need for separate memory units and data transfer interfaces. This integration allows data to be processed directly where it is stored, eliminating the von Neumann bottleneck and reducing energy consumption associated with data movement between memory and processing units.
Solution Approach 2:
The patent replaces traditional von Neumann architecture with a logic gate-based neural network implementation. Instead of using sequential processing with memory access, the neural network uses parallel logic gates that can process multiple inputs simultaneously. The logical connectors establish direct logical relationships between neurons, enabling parallel computation that overcomes the sequential processing limitations of traditional architectures.
2Ease of operation
If neural networks use sequential evaluation, then implementation is simplified, but inference time becomes high
Solution Approach 1:
The patent segments the neural network into discrete logic gates and logical connectors that can operate independently and in parallel. Each logic gate processes its inputs simultaneously, and the logical connectors establish parallel data paths between different parts of the network. This segmentation enables parallel processing of multiple computations at the same time, dramatically reducing inference time compared to sequential evaluation while maintaining relatively simple implementation through standardized logic gate components.
Solution Approach 2:
The patent transitions from sequential time-based processing to parallel space-based processing. Instead of processing neurons one after another in time, the neural network architecture allows multiple neurons to process simultaneously in parallel. The logical connectors create spatial parallelism by establishing multiple data paths that operate concurrently, transforming the processing dimension from temporal sequence to spatial parallelism.
3Productivity
If data is moved between memory and processing units, then data can be accessed, but computational throughput is limited
Solution Approach 1:
The patent combines memory and processing units into a single integrated neural network circuit. The logic gates that perform computation are physically located within the same chip as the data storage elements, eliminating the need for data movement between separate memory and processing units. Data is processed in-place, and the logical connectors establish direct logical relationships that eliminate data transfer delays.
Solution Approach 2:
The patent introduces logical connectors as intermediaries that establish direct logical relationships between neurons without requiring physical data movement. The logical connectors mediate the connection between input and output neurons, enabling information flow through logical operations rather than data transfer, thereby eliminating data movement time while maintaining computational functionality.
Data Source
AI summary
A deep neural network circuit with multiple layers formed of multi-terminal logic gates is provided. In one aspect, the neural network circuit includes a plurality of logic gates arranged into a plurality of layers and a plurality of logical connectors arranged between each pair of adjacent layers. Each of the logical connectors connects the output of a first logic gate to the input of a second logic gate and each of the logical connectors has one of a plurality of different logical connector states. The neural network circuit is configured to be trained to implement a function by finding a set of the logical connector states for the logical connectors such that the neural network circuit implements the function.