Neural Network Processor DMA Buffering for Lower CPU Bus Load

Solution Overview

Problem

The frequent initiation of CPU instructions to read weight parameters and data from higher-level buffers or external memory in neural network processors leads to increased CPU bus bandwidth usage, power consumption, and reduced computational efficiency.

Innovation Solution

Incorporating a direct memory access controller in the processor core to directly access higher-level buffers or external memory, reducing the need for frequent CPU instruction initiation and improving reading speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If CPU instructions are frequently initiated to read weight parameters and data from higher-level buffers or external memory, then data can be read from memory, but CPU bus bandwidth usage increases and computational efficiency decreases

Engineering Contradiction:

Improvecomputational efficiencyVSAvoidCPU bus bandwidth usage

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent segments the data reading function by introducing a dedicated DMA controller within the processor core that operates independently from the CPU. This allows data reading operations to be separated from CPU instruction execution, enabling parallel operation and reducing CPU bus bandwidth usage while maintaining computational efficiency.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a DMA controller as an intermediary component between the processor core and memory systems. This intermediary handles data transfer operations independently, eliminating the need for frequent CPU instruction initiation and reducing the burden on CPU bus bandwidth while improving overall system efficiency.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If CPU instructions are frequently initiated to read weight parameters and data, then data can be read from memory, but system power consumption increases

Engineering Contradiction:

Improvedata reading speedVSAvoidsystem power consumption

Core Design Contradiction:

ProductivityVSUse of energy by stationary object

Solution Approach 1:

The patent segments the data reading function by introducing a dedicated DMA controller within the processor core that operates independently from the CPU. This allows data reading operations to be separated from CPU instruction execution, enabling parallel operation and reducing CPU bus bandwidth usage while maintaining computational efficiency.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a DMA controller as an intermediary component between the processor core and memory systems. This intermediary handles data transfer operations independently, eliminating the need for frequent CPU instruction initiation and reducing the burden on CPU bus bandwidth while improving overall system efficiency.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Reliability

If CPU instructions are frequently initiated to read weight parameters and data, then data can be read from memory, but computational efficiency of the neural network processor is reduced

Engineering Contradiction:

Improvedata access accuracyVSAvoidcomputational efficiency

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent segments the data reading function by introducing a dedicated DMA controller within the processor core that operates independently from the CPU. This allows data reading operations to be separated from CPU instruction execution, enabling parallel operation and reducing CPU bus bandwidth usage while maintaining computational efficiency.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a DMA controller as an intermediary component between the processor core and memory systems. This intermediary handles data transfer operations independently, eliminating the need for frequent CPU instruction initiation and reducing the burden on CPU bus bandwidth while improving overall system efficiency.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS20260093970A1Neural network processor, system-on-a-chip, data processing method, and storage medium

Publication Date: 2026.04.02 BEIJING HORIZON ROBOTICS TECH RES & DEV CO LTD

AI summary

Disclosed are a neural network processor, a system-on-a-chip, a data processing method, and a storage medium, relating to the technical field of systems-on-a-chip. The neural network processor includes a first processor core, where the processor core includes: a first buffer, configured to buffer a first input tensor corresponding to a first neural network layer in the neural network model; a first direct memory access controller, configured to read a second input tensor corresponding to the first neural network layer from a second buffer, and write the second input tensor into an operational array; and the operational array, configured to read the first input tensor from the first buffer, and perform a first operation based on the first input tensor and the second input tensor, to obtain a first output tensor.