DRAM ODT Resistance Training for Per-Chip and DQ Signal Integrity
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Solution Overview
Problem
Conventional DRAM devices struggle to adjust on-die termination (ODT) resistance values for each chipset or DQ within a DRAM module, leading to signal reflection and reduced signal integrity, particularly in high-capacity memory systems like servers.
Innovation Solution
A DRAM device with a memory controller that measures and sets ODT resistance values individually for each rank, chipset, and DQ, using a mode register set and training to ensure optimal impedance matching, thereby minimizing signal reflection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single ODT resistance value is adjusted in the DRAM device, then the device complexity is reduced, but signal integrity deteriorates due to inability to adjust ODT resistance for each chipset or DQ
Solution Approach 1:
The patent segments the ODT resistance adjustment capability by introducing separate control registers for each chipset and DQ group. This allows independent adjustment of ODT resistance values for different signal paths, improving signal integrity for each segment while maintaining manageable device complexity through structured organization.
Solution Approach 2:
The patent implements local quality by enabling different ODT resistance values to be set for different chipsets and DQ groups based on their specific signal characteristics. Each chipset/DQ can have optimized termination resistance tailored to its local signal integrity requirements, rather than using a uniform value across the entire device.
2Reliability
If ODT resistance value is adjusted for each chipset or DQ, then signal integrity is improved, but the ease of operation deteriorates due to multiple adjustment parameters
Solution Approach 1:
The patent implements a universal training mechanism that automatically measures signal characteristics and determines optimal ODT resistance values for all chipsets and DQ groups. This multi-functional training process handles multiple adjustment parameters systematically, improving ease of operation while maintaining the ability to optimize signal integrity for each chipset/DQ.
Solution Approach 2:
The patent incorporates feedback through an automatic training process that measures signal quality metrics and uses this information to adjust ODT resistance values. The memory controller performs training operations, measures response characteristics, and automatically configures optimal resistance values, eliminating manual adjustment complexity while achieving superior signal integrity.
3Productivity
If conventional ODT resistance adjustment is used, then device complexity is low, but signal reflection increases leading to reduced computational performance
Solution Approach 1:
The patent performs preliminary action by conducting training operations before normal memory operations to pre-determine optimal ODT resistance values. This preliminary measurement and configuration phase establishes proper impedance matching for each chipset and DQ group, preventing signal reflection issues before they affect computational performance during actual operation.
Data Source
AI summary
Disclosed are a dynamic random access memory (DRAM) device, an on-die termination (ODT) resistance value setting method thereof, and a computer program therefor, and the DRAM device includes at least one DRAM module and a memory controller configured to measure a resistance value of an ODT resistor corresponding to one of a rank included in the DRAM module, a chipset included in the rank, and a DQ included in the chipset and set a resistance value of an ODT resistor corresponding to one of the rank, the chipset, and the DQ on the basis of the measured resistance value.