DRAM-Based Reconfigurable Logic for PLDs
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Solution Overview
Problem
Traditional programmable logic devices (PLDs) require high voltage for reconfiguration, which is inefficient and costly, and often result in lower density and higher production costs due to the need for specialized programming methods.
Innovation Solution
A reconfigurable look-up table based on dynamic random access memory (DRAM) sub-arrays that can be reprogrammed using standard memory access operations, eliminating the need for high voltage and allowing for dynamic reconfiguration of logic functions without altering the underlying hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional PLDs use SRAM or EEPROM for programming, then they can store configuration data, but they require high voltage to break or set electrical connections, increasing power consumption and manufacturing complexity
Solution Approach 1:
The patent changes the voltage parameter from high voltage (traditional PLD programming) to standard low voltage (DRAM operations). By using standard DRAM write operations instead of high-voltage programming, the system achieves configuration storage without the energy-intensive voltage switching, directly resolving the contradiction between reliable configuration storage and low power consumption
2Adaptability or versatility
If traditional PLDs use fixed logic circuits, then they have simple structure, but they lack reconfigurability and adaptability
Solution Approach 1:
The patent makes the DRAM array universal by enabling it to serve dual purposes: traditional memory storage and reconfigurable logic implementation. By loading lookup tables into the DRAM array, the same physical structure can function as either memory or programmable logic, achieving high adaptability without increasing structural complexity
Solution Approach 2:
The patent introduces dynamic reconfigurability where the logic function can be changed at runtime by writing new lookup tables to the DRAM array. This dynamic capability allows the system to adapt its functionality on-the-fly, transforming a static structure into a dynamically reconfigurable one that balances simplicity with versatility
3Adaptability or versatility
If traditional PLDs use high voltage programming, then they can reconfigure logic functions, but the process is costly and inefficient
Solution Approach 1:
The patent changes the voltage parameter from high voltage programming to standard DRAM voltage levels. This parameter change eliminates the need for specialized high-voltage programming circuits and processes, simplifying manufacturing and reducing production costs while maintaining full reconfiguration capability through standard memory write operations
4Ease of operation
If traditional PLDs use specialized programming circuits, then they can program logic devices, but they increase device complexity and manufacturing difficulty
Solution Approach 1:
The patent eliminates specialized programming circuits by making the DRAM array itself programmable through standard memory operations. The same DRAM cells that store data also store lookup tables for logic functions, removing the need for separate programming circuits and reducing overall device complexity while maintaining full programming capability
Solution Approach 2:
The DRAM array serves itself by using its inherent write capability to program its own contents as lookup tables. Instead of requiring external specialized programming circuits, the memory array programmatically configures itself through standard write operations, simplifying the overall system architecture
Data Source
AI summary
According to one general aspect, an apparatus may include a memory array comprising a plurality of memory sub-arrays. At least one of the sub-arrays may be arranged as a reconfigurable look-up table. The reconfigurable look-up table may include: a plurality of memory cells configured to store data, a local row decoder configured to activate one or more rows of memory cells based upon a set of input signals, a local line selector configured to select a sub-set of the row of memory cells based upon at least one input signal.