DRAM Refresh Circuit for Stable Word Line Selection
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Solution Overview
Problem
In Dynamic Random Access Memory (DRAM) with non-binary structural capacity, the varying number of word lines selected during refresh operations leads to unstable refresh currents, affecting performance and causing interference with the power supply.
Innovation Solution
A refresh circuit comprising a refresh counter, address mixer, and address pre-decoding circuit ensures a fixed number of word lines are turned on during each refresh operation by generating preset bank address selection signals and row address selection signals, stabilizing the refresh current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If different memory cells are selected through word lines and bit lines in DRAM refresh operations, then memory cells can be accessed and refreshed, but the refresh current fluctuates due to varying numbers of word lines selected
Solution Approach 1:
The patent applies dynamics by making the word line selection dynamic based on the refresh counter state. The mixer circuit dynamically selects which word lines to activate during each refresh cycle, ensuring that the total number of activated word lines remains constant even though the specific lines change. This dynamic selection process maintains refresh current stability while still allowing different memory cells to be refreshed.
Solution Approach 2:
The patent changes the parameter of word line selection by using the mixer circuit to transform the refresh counter output into a fixed number of activated word lines. The mixer circuit modifies the selection parameters dynamically, ensuring that regardless of which specific word lines are selected, the total count remains constant, thereby stabilizing the refresh current while maintaining refresh coverage.
2Stability of the object's composition
If a fixed number of word lines are selected during each refresh operation, then refresh current stability is improved, but the ability to refresh different memory cells varies
Solution Approach 1:
The mixer circuit provides dynamic word line selection based on the refresh counter state, ensuring that different combinations of word lines are selected in different refresh cycles while maintaining a fixed total number of activated word lines. This dynamic yet constrained selection approach balances refresh current stability with comprehensive memory cell coverage.
Solution Approach 2:
The refresh operation uses periodic action through the refresh counter that cycles through different memory cell selections. The mixer circuit ensures that each period (refresh cycle) activates a fixed number of word lines, while over multiple periods, different memory cells are covered. This periodic selection with fixed activation count maintains current stability while achieving comprehensive refresh.
3Adaptability or versatility
If refresh operations select varying numbers of word lines, then different memory regions can be refreshed, but interference with the power supply occurs due to current fluctuations
Solution Approach 1:
The mixer circuit dynamically adjusts the word line selection to maintain a constant number of activated word lines during each refresh operation. This dynamic adjustment prevents refresh current fluctuations that would otherwise cause power supply interference, while still allowing different memory regions to be refreshed by changing which specific word lines are selected based on the refresh counter state.
Solution Approach 2:
The patent converts the potential harm of refresh current fluctuations into a benefit by using the mixer circuit to transform variable word line selections into a fixed activation count. The mixer takes the varying refresh requirements and transforms them into a stable current draw pattern, eliminating power supply interference while maintaining the ability to refresh different memory regions.
Data Source
AI summary
A refresh circuit includes a refresh counter configured to output address signals through a plurality of address pins; an address mixer configured to output row address selection signals according to the address signals received by the row address pins, output first bank address signals according to the address signals received by bank address pins, receive a refresh signal and a power supply voltage signal, and output fixed second bank address signals according to the refresh signal and the power supply voltage signal; and an address pre-decoding circuit configured to output a preset number of bank address selection signals according to the first bank address signals and the second bank address signals.