DRAM Row Hammer Control Through Adaptive Pre-Charge Timing

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Solution Overview

Problem

Dynamic random access memory (DRAM) systems experience intermittent failures due to row hammer events, where repeated access to a single memory cell row disturbs adjacent cells, leading to data corruption, and existing solutions like target refresh operations require complex refresh circuits and generate scheduling loads.

Innovation Solution

A memory device that adjusts pre-charge preparation time, reroutes rows, or blocks commands based on the type of row hammer, determined by the ratio of active to write/read commands, to alleviate row hammer effects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If target refresh operation is used to refresh memory cells affected by row hammer, then data corruption is prevented, but the refresh circuit becomes complex and scheduling load increases

Engineering Contradiction:
Improvedata integrityVSAvoidrefresh circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the row hammer mitigation function from the traditional refresh circuit by implementing a separate monitoring mechanism that counts active commands and write/read commands. This separate monitoring unit identifies row hammer conditions and triggers selective pre-charge operations without requiring a complex dedicated refresh circuit, thus preventing data corruption while simplifying the overall circuit design.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The memory device performs self-diagnosis by monitoring its own command patterns and automatically detecting row hammer conditions through counting operations. When row hammer is detected, the system self-corrects by executing pre-charge operations on affected rows without external intervention, eliminating the need for complex external refresh control circuits.

Inventive Principle:
Principle #25Self-service

2Reliability

If target refresh operation is used to refresh memory cells affected by row hammer, then data corruption is prevented, but scheduling load and switching load between tasks increases

Engineering Contradiction:
Improvedata integrityVSAvoidscheduling efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system performs preliminary monitoring of command patterns continuously in the background, counting active commands and write/read commands to detect row hammer conditions before they cause data corruption. This early detection allows the system to execute pre-charge operations proactively, preventing the need for urgent refresh scheduling and reducing task switching overhead.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The memory device autonomously monitors its own operation patterns and automatically executes pre-charge operations when row hammer conditions are detected, without requiring external controller intervention or complex scheduling algorithms. This self-managing approach reduces the scheduling burden on external controllers and improves overall system productivity.

Inventive Principle:
Principle #25Self-service

3Quantity of substance

If cell size is decreased to boost DRAM capacity and integration, then memory capacity increases, but susceptibility to row hammer events increases

Engineering Contradiction:
Improvememory capacityVSAvoidrow hammer susceptibility
Core Design Contradiction:
Quantity of substanceVSObject-affected harmful factors

Solution Approach 1:

The patent segments the monitoring function into separate counters for active commands and write/read commands, allowing precise tracking of access patterns to specific memory rows. This segmented monitoring approach enables the system to detect row hammer conditions in densely integrated memory cells without requiring changes to the physical cell structure, thus maintaining high capacity while improving resistance to row hammer attacks.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12437794B2Method of controlling row hammer and a memory device
Publication Date: 2025.10.07 SAMSUNG ELECTRONICS CO LTD
  • US12437794B2 patent drawing
  • US12437794B2 patent drawing
  • US12437794B2 patent drawing

AI summary

A memory device including: a memory cell array including memory cell rows; and a control logic circuit to perform a row, write, read, or pre-charge operation on the memory cell rows in response to an active, write, read, or pre-charge command, wherein the control logic circuit is further configured to: calculate a first count value by counting the active command and a second count value by counting the write command or the read command, with respect to a first memory cell row, during a row hammer monitor time frame; determine a type of row hammer of the first memory cell row based on a ratio of the first count value to the second count value; and adjust a pre-charge preparation time between an active operation and the pre-charge operation, by changing a pre-charge operation time point according to the determined type of row hammer.