DRAM On-Die Termination Switching for Impedance Matching
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Solution Overview
Problem
High-speed signaling systems with single on-die termination schemes suffer from impedance discontinuity and signal attenuation, leading to sub-optimal performance and increased error rates due to impedance mismatch and reflection issues.
Innovation Solution
Implementing multiple, graduated on-die termination structures per high-speed signaling line, allowing for switchable selection between high-load (hard) and low-load (soft) terminations based on whether the memory module is the destination for incoming signals, thereby optimizing impedance matching and energy absorption without attenuating incoming signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single on-die termination structure is used, then the device complexity is reduced, but impedance matching and signal quality deteriorate due to impedance discontinuity and reflection issues
Solution Approach 1:
The patent divides the termination structure into multiple segments (first and second termination structures) with different load values. Each segment can be independently controlled to provide appropriate termination for different operating conditions, thereby improving signal quality without excessive complexity increase.
Solution Approach 2:
The patent implements dynamic switching between different termination structures based on operational mode (read vs. write operations). The termination control circuit dynamically selects which termination structure to activate, allowing the system to adapt to changing impedance requirements and eliminate reflections during both read and write operations.
2Object-affected harmful factors
If termination load is increased to match impedance, then reflection is reduced, but signal attenuation increases
Solution Approach 1:
The patent applies different termination load values to different termination structures based on the specific operational requirements. The first termination structure uses a first load value optimized for read operations, while the second termination structure uses a second load value optimized for write operations, allowing each structure to provide optimal reflection cancellation without excessive attenuation for its specific use case.
Solution Approach 2:
The patent changes the termination load parameter based on the operational mode. By switching between different load values (first load value for reads, second load value for writes), the system optimizes the balance between impedance matching and signal strength for each type of operation, reducing reflections while minimizing energy loss.
3Reliability
If on-die termination is enabled for all operations, then impedance matching improves, but signal attenuation increases during read operations
Solution Approach 1:
The patent dynamically controls the termination structures based on the operational mode detected by the termination control circuit. During read operations, only the first termination structure with the first load value is activated to provide impedance matching without excessive attenuation. During write operations, the second termination structure with the second load value is activated. This dynamic switching ensures optimal impedance matching for each operation type while minimizing unnecessary signal attenuation.
Solution Approach 2:
The patent applies termination selectively to match local operational requirements. The first termination structure provides localized impedance matching for read operations, while the second termination structure provides localized impedance matching for write operations. This selective application of termination quality ensures that each operation receives the appropriate level of termination without the drawbacks of universal termination.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances signaling margins, reduces bit error rates, and provides additional headroom for increased signaling rates by dynamically adjusting terminations to match the impedance of the selected memory module, thus improving overall system performance.
Implementation Method 1
terminating elements have been implemented by discrete resistors connected to metal traces on a mother board or other printed circuit board
Data Source
AI summary
An integrated circuit device transmits, to a dynamic random access memory device (DRAM), a write command indicating that write data is to be sampled by a data interface of the DRAM, and a plurality of commands that specify programming a plurality of control values into a plurality of corresponding registers in the DRAM. The plurality of control values include first and second control values that indicate respective first and second terminations that the DRAM is to apply to the data interface during a time interval that begins a predetermined amount of time after the DRAM receives the write command, the first termination to be applied during a first portion of the time interval while the data interface is sampling the write data and the second termination to be applied during a second portion of the time interval after the write data is sampled.