DRAM Variable Burst Lengths for Data and Metadata Access
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional DRAM devices restrict efficient access to data and metadata, limiting the ability to store additional metadata for security and reliability purposes without accessing multiple cache lines.
Innovation Solution
A DRAM device with variable burst lengths and two modes of operation, allowing programmable settings to adjust burst lengths and column address ranges, incorporating on-die error correction code (ECC) and circuitry to manage metadata and data access efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional DRAM core architecture is used, then device complexity is reduced, but the ability to store and access metadata efficiently is limited
Solution Approach 1:
The patent implements dynamic burst length configuration where the DRAM device can switch between different burst lengths (e.g., 8, 16, 32, 64) based on operational mode. This is achieved through programmable control logic that adjusts the number of cache lines accessed per transaction, allowing the system to adapt between metadata mode (longer bursts) and capacity mode (shorter bursts) without requiring multiple fixed architectures
Solution Approach 2:
The patent creates a universal DRAM core architecture that can perform multiple functions by configuring the same physical resources differently. The same memory array and data paths can operate in metadata mode (accessing multiple cache lines with extended burst lengths) or capacity mode (standard access patterns), eliminating the need for separate dedicated hardware for each function
2Productivity
If burst length is extended to transmit metadata simultaneously with data, then data access efficiency is improved, but column address range increases
Solution Approach 1:
The patent utilizes the time dimension by implementing extended burst lengths that access multiple cache lines sequentially within a single transaction. Instead of expanding spatial dimensions (more parallel channels), the system extends the temporal dimension of data transfer, allowing metadata and data to be transmitted over the same physical channels across multiple clock cycles
3Adaptability or versatility
If variable burst lengths are implemented, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent implements programmable control registers that allow software to configure burst length parameters directly. By exposing configurable parameters (burst length, cache line count) through standard interfaces, the complex control logic can be programmed and adjusted without hardware redesign, simplifying the physical implementation while maintaining high adaptability
Data Source
AI summary
Technologies for dynamic random access memory (DRAM) devices with variable burst lengths are described. One DRAM device includes a first mode of operation having a first burst length and a first column address range and a second mode of operation having a second burst length and a second column address range. Only one of the first burst length and the second burst length is a power of two. A first product of the first column address range and the first burst length and a second product of the second column address range and the second burst length are substantially the same. The DRAM device includes an error correction code (ECC) block to generate, receive, and store ECC parity associated with data in the first mode of operation and the second mode of operation.