DRAM Word Line Contact Layout With Insulating Walls
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Solution Overview
Problem
As semiconductor devices, such as DRAM, are miniaturized to increase data storage capacity, the reduction in wiring pitch and distance between word lines leads to potential short-circuiting of adjacent word lines due to increased contact hole diameters during the formation of contact holes.
Innovation Solution
The formation of insulating walls above the word lines in the memory cell array region and peripheral regions, along with precise etching techniques to create word line contact holes with controlled dimensions, prevents short-circuiting by maintaining the position of word line contact electrodes and suppressing lateral displacement during the filling of conductive material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the diameter of contact holes is increased to facilitate formation, then the contact holes become easier to form, but adjacent word lines may be short-circuited
Solution Approach 1:
The patent divides the contact hole formation process into multiple stages: first forming a mandrel pattern, then using it as a mask to etch the contact holes. This segmentation allows precise control of contact hole dimensions and positioning, preventing short circuits while maintaining ease of manufacture through the systematic multi-step approach
Solution Approach 2:
The patent introduces a mandrel as an intermediary structure that facilitates the formation of contact holes with precise dimensions. The mandrel serves as a temporary template that enables accurate contact hole placement without directly becoming part of the final device, thus preventing short circuits while simplifying the overall manufacturing process
2Quantity of substance
If the wiring pitch is reduced to increase storage capacity, then the data storage capacity increases, but the distance between word lines decreases leading to potential short circuits
Solution Approach 1:
The patent applies different properties to different regions: insulating walls are formed specifically in regions where short circuits might occur between adjacent contact holes or word lines, while other regions maintain their original structure. This localized application of insulation precisely addresses the short circuit risk without affecting the overall miniaturization and storage capacity
Solution Approach 2:
The patent addresses the two-dimensional packing density issue by introducing a vertical dimension - forming insulating walls that extend upward from the substrate surface. This third dimension provides additional isolation between adjacent structures, enabling closer horizontal spacing of word lines and contact holes while maintaining reliability
3Manufacturing precision
If precise etching techniques are used to control contact hole dimensions, then the position accuracy of word line contact electrodes is improved, but the manufacturing process complexity increases
Solution Approach 1:
The patent performs preliminary actions by first forming the mandrel pattern and insulating walls before etching the contact holes. These preliminary structures serve as guides and masks that automatically define the precise position and dimensions of contact holes, eliminating the need for complex real-time etching control while achieving high manufacturing precision
4Reliability
If insulating walls are formed above word lines to prevent short circuits, then the reliability is improved, but the device complexity increases
Solution Approach 1:
The patent merges multiple functions into the insulating walls: they serve as both the isolation structure to prevent short circuits and as a mask/template for forming contact holes. This combination reduces the need for separate structures or processes, thereby improving reliability without proportionally increasing device complexity
Data Source
AI summary
An apparatus includes a plurality of memory cells in a memory cell array region; a plurality of word lines extending across the memory cell array region and a peripheral region in which no memory cell is arranged; a plurality of contact plugs on even numbered ones of the plurality of word lines in the peripheral region, respectively; and a plurality of insulating walls on odd numbered ones of the plurality of word lines in the peripheral region, respectively.